In one example, an apparatus comprises: a memory array having an array of memory elements arranged in rows and columns, each memory element being configured to store a data element; and a memory access circuit configured to: perform a row write operation to store a first group of data elements at a first row of the array of memory elements; perform a column read operation at a first column of the array of memory elements to obtain a second group of data elements; and perform a column write operation to store a third group of data elements at the first column of the array of memory elements to replace the second group of data elements.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The apparatus of claim 1, wherein the read operations in the first orientation and the write operations in the first orientation are performed in an alternating manner.
4. The apparatus of claim 1, wherein each of the first memory and the second memory includes an array of memory elements arranged in rows and columns.
10. The method of claim 9, wherein the read operations in the first orientation and the write operations in the first orientation are performed in an alternating manner.
11. The method of claim 9, wherein each of the first memory and the second memory includes an array of memory elements arranged in rows and columns.
17. The non-transitory computer-readable medium of claim 16, wherein the read operations in the first orientation and the write operations in the first orientation are performed in an alternating manner.
18. The non-transitory computer-readable medium of claim 16, wherein each of the first memory and the second memory includes an array of memory elements arranged in rows and columns.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 28, 2022
November 12, 2024
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