A memory control circuit and a refresh method for a dynamic random access memory (DRAM) array are provided. The memory control circuit includes a mode register circuit, a command decoder and a refresh circuit. The mode register circuit includes a plurality of mode registers. The command decoder receives a refresh command and sets a flag of a target mode register corresponding to the refresh command among the plurality of mode registers to a setting value. The refresh circuit refreshes the DRAM array in response to the refresh command through the command decoder and the setting value of the flag of the target mode register.
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3. The memory control circuit of claim 1, wherein the command decoder identifies the refresh command to obtain a refresh mode and generates an address data of the setting signal, wherein the address data corresponds to the target mode register.
4. The memory control circuit of claim 1, wherein a time length required to set the flag to the setting value by the command decoder is shorter than a cycle time of a mode register command delay.
5. The memory control circuit of claim 1, wherein when the refresh command is a same bank refresh command, the command decoder set the flag of the target mode register corresponding to the same bank refresh command to the setting value, so that the memory control circuit operates in a fine granular refresh (FGR) mode.
8. The refresh method of claim 6, wherein a time length required to set the flag to the setting value is shorter than a cycle time of a mode register command delay.
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September 13, 2022
November 12, 2024
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