Apparatuses and systems for pedestals are provided. An example pedestal may have a body with an upper annular seal surface that is planar, perpendicular to a vertical center axis of the body, and has a radial thickness, a lower recess surface offset from the upper annular seal surface, and a plurality of micro-contact areas (MCAs) protruding from the lower recess surface, each MCA having a top surface offset from the lower recess surface by a second distance less, and one or more electrodes within the body. The upper annular seal surface may be configured to support an outer edge of a semiconductor substrate when the semiconductor substrate is being supported by the pedestal, and the upper annular seal surface and the tops of the MCAs may be configured to support the semiconductor substrate when the semiconductor substrate is being supported by the pedestal.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor processing system of claim 1, wherein a seal is created between the upper annular seal surface and the semiconductor substrate as part of the semiconductor substrate being supported by the electrostatic chuck.
3. The semiconductor processing system of claim 1, wherein the upper annular seal surface has an inner radius that is less than the radius of the semiconductor substrate, and an outer radius that is greater than the radius of the semiconductor substrate.
4. The semiconductor processing system of claim 3, wherein the inner radius is about 142 millimeters.
5. The semiconductor processing system of claim 4, wherein the outer radius is about 150 millimeters.
6. The semiconductor processing system of claim 1, wherein the radial thickness is less than or equal to about 25 millimeters.
7. The semiconductor processing system of claim 6, wherein the radial thickness is less than or equal to about 15 millimeters.
9. The semiconductor processing system of claim 8, wherein the first distance and the second distance are equal to or between 0.0127 millimeters and 0.0381 millimeters.
10. The semiconductor processing system of claim 9, wherein the first distance and the second distance are 0.0254 millimeters.
11. The semiconductor processing system of claim 1, wherein the first distance is greater than the second distance.
12. The semiconductor processing system of claim 11, wherein the first distance and the second distance are equal to or between 0.0127 millimeters and 0.0381 millimeters.
13. The semiconductor processing system of claim 1, wherein the plurality of MCAs includes more than 2,000 MCAs.
14. The semiconductor processing system of claim 13, wherein the plurality of MCAs includes more than 4,000 MCAs.
15. The semiconductor processing system of claim 13, wherein substantially all the MCAs are spaced equally from each other.
16. The semiconductor processing system of claim 15, wherein substantially all the MCAs are spaced from each other by 3.9 millimeters.
19. The semiconductor processing system of claim 1, wherein each MCA is a cylinder that has a planar top surface area.
20. The semiconductor processing system of claim 19, wherein the radius of each MCA is about 0.35 millimeters.
21. The semiconductor processing system of claim 1, wherein the upper annular seal surface has a surface roughness between about 0.8128 microns and about 0.2032 microns.
22. The semiconductor processing system of claim 1, wherein each MCA has a top surface having a roughness between about 0.8128 microns and about 0.2032 microns.
23. The semiconductor processing system of claim 1, wherein the upper annular seal surface has a flatness having a maximum range of 0.0254 millimeters.
24. The semiconductor processing system of claim 1, wherein each MCA has a top surface having a flatness having a maximum range of 0.0254 millimeters.
25. The semiconductor processing system of claim 1, wherein the body comprises a ceramic.
31. The semiconductor processing system of claim 1, wherein the power supply is configured to apply voltage in a range of 300 V to 1000 V to the at least one of the one or more electrodes to induce the electrostatic clamping force.
32. The semiconductor processing system of claim 1, wherein the second distances of the MCAs are sized to correspond with a non-zero curvature of the semiconductor substrate.
33. The semiconductor processing system of claim 32, wherein the second distances of the MCAs are sized such that the non-zero curvature of the semiconductor substrate is maintained while at least the electrostatic clamping force is applied to the semiconductor substrate.
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April 4, 2019
November 12, 2024
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