Patentable/Patents/US-12142552
US-12142552

Lead frame for a package for a semiconductor device, semiconductor device and process for manufacturing a semiconductor device

PublishedNovember 12, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A lead frame for an integrated electronic device includes a die pad made of a first metallic material. A top coating layer formed by a second metallic material is arranged on a top surface of the die pad. The second metallic material has an oxidation rate lower than the first metallic material. The top coating layer leaves exposed a number of corner portions of the top surface of the die pad. A subsequent heating operation, for example occurring in connection with wirebonding, causes an oxidized layer to form on the corner portions of the top surface of the die pad at a position in contact with the top coating layer.

Patent Claims
10 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The integrated electronic device according to claim 1, wherein each corner portion has a squared shape.

3

3. The integrated electronic device according to claim 1, further comprising a plurality of pads having top surfaces coated by coating regions made of the second metallic material.

5

5. The integrated electronic device according to claim 4, wherein each corner portion has a squared shape.

6

6. The integrated electronic device according to claim 4, further comprising a plurality of pads having top surfaces coated by coating regions made of the second metallic material.

8

8. The integrated electronic device according to claim 7, wherein the further top coating layer does not cover top surfaces of the tie bars and wherein said oxidized region coats top surfaces of the tie bars.

9

9. The integrated electronic device according to claim 7, wherein the inner frame and the outer frame have different heights, and wherein each tie bar includes a corresponding slanted portion to transition between said different heights.

10

10. The integrated electronic device according to claim 7, wherein each corner portion has a squared shape.

11

11. The integrated electronic device according to claim 7, further comprising a plurality of pads having top surfaces coated by coating regions made of the second metallic material.

13

13. The integrated electronic device according to claim 12, wherein the top coating structure includes a top coating region covering the die pad; and wherein said corner portions are formed by the die pad, which has a squared shape.

14

14. The integrated electronic device according to claim 13, wherein the die pad structure further includes a ground ring laterally surrounding the die pad and having the shape of a squared frame; and wherein the top coating structure includes an additional top coating layer covering the ground ring; and wherein said corner portions are formed by the ground ring.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

November 28, 2022

Publication Date

November 12, 2024

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Cite as: Patentable. “Lead frame for a package for a semiconductor device, semiconductor device and process for manufacturing a semiconductor device” (US-12142552). https://patentable.app/patents/US-12142552

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Lead frame for a package for a semiconductor device, semiconductor device and process for manufacturing a semiconductor device — Fulvio Vittorio Fontana | Patentable