A mask structure, a semiconductor structure and methods for manufacturing the same are disclosed. The method for manufacturing the mask structure includes: forming a pattern transfer layer, a first etching stop layer, a first sacrificial layer and a first hard mask layer sequentially stacked from bottom to top; patterning the first sacrificial layer and the first hard mask layer, to obtain a first sacrificial pattern, the first sacrificial pattern exposing the first etching stop layer; forming a first initial mask pattern on side walls of the first sacrificial pattern; removing the first sacrificial pattern; removing, based on the first initial mask pattern, a part of the first etching stop layer of which a top surface being exposed; removing the first initial mask pattern, and using the remaining part of the first etching stop layer on the upper surface of the pattern transfer layer as a first mask pattern.
Legal claims defining the scope of protection, as filed with the USPTO.
7. The method according to claim 5, wherein the second filling layer and the first filling layer are both formed by a spin coating.
8. The method according to claim 4, wherein when the part of the second etching stop layer of which a top surface being exposed is removed, an etching selection ratio of the second etching stop layer to the first filling layer is 3:1 to 10:1.
9. The method according to claim 1, wherein when the part of the first etching stop layer of which a top surface being exposed is removed, an etching selection ratio of the first etching stop layer to the pattern transfer layer is 5:1 to 50:1.
13. The method according to claim 12, wherein a surface of the substrate has a conductive contact pad, and the to-be-etched material layer comprises a dielectric layer.
14. The method according to claim 13, wherein the blind holes comprise capacitor holes, bottoms of the blind holes expose the conductive contact pad.
17. A semiconductor structure, manufactured by the method according to claim 12.
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January 14, 2022
November 19, 2024
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