A semiconductor device includes a memory cell array including a plurality of memory cells, a bit line selection circuit, including a first main select transistor, and a plurality of first sub-select transistors connected in parallel with each other, and the plurality of first sub-select transistors configured to be the first memory cell through the first bit line to transfer the read current from the first bit line to the first memory cell; and a sense amplifier configured to compare a reference current having a predetermined current value with a memory current drawn by the first memory cell, and output an output signal based on an input voltage, the sense amplifier including an active load, connected to the first main select transistor, comprising a PMOS diode or a NMOS diode configured to lower the input voltage at a sense node.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The semiconductor device of claim 1, wherein the plurality of first sub-transistors are disposed between the first main select transistor and the bit line.
8. An embedded flash memory comprising the semiconductor device of claim 1.
12. An embedded flash memory comprising the semiconductor device of claim 9.
14. The embedded flash memory of claim 13, wherein when a memory current of the memory currents is greater than the reference current, the input voltage at the sense node decreases.
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March 17, 2022
November 26, 2024
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