A memory device is provided. The memory device comprises a first plane and a second plane. The memory device further comprises a control circuit coupled to the first plane and the second plane. The control circuit is configured to: simultaneously initiate programming the first plane and the second plane; and in response to the first plane being successfully programmed, the second plane being unsuccessfully programmed, and a programming pulse count of the second plane being less than a predetermined programming pulse count value, keep programming the second plane and disable the first plane.
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February 27, 2023
November 26, 2024
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