A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The semiconductor device of claim 1, wherein the data alignment circuit is configured to perform a domain crossing operation of aligning the first group and second group of the input data in synchronization with the first to third internal strobe signals and generating the internal data from at least any one of the aligned first group and second group of the input data in synchronization with the latch clock.
4. The semiconductor device of claim 1, wherein the data alignment circuit is configured to align the first group and second group of the input data and generate the internal data from the aligned first group and second group of the input data, after a start of the first operation mode.
5. The semiconductor device of claim 1, wherein the data alignment circuit is configured to align the first group of the input data and generate the internal data from the aligned first group of the input data, after a start of the second operation mode.
6. The semiconductor device of claim 1, wherein in a continuous operation of the first operation mode and the second operation mode, the first write data and the second write data have an identical data window.
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September 23, 2022
November 26, 2024
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