A semiconductor package includes; a first redistribution structure including first redistribution conductors, a semiconductor chip on the first redistribution structure and including connection pads electrically connecting the first redistribution conductors, a connection conductor on the first redistribution structure, laterally spaced apart from the semiconductor chip, and electrically connected to the first redistribution conductors, an encapsulant on the first redistribution structure and sealing the semiconductor chip and at least a portion of the connection conductor, a barrier layer extending along an upper surface of the encapsulant, and a second redistribution conductor on the barrier layer and penetrating the barrier layer to contact the connection conductor.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The semiconductor package of claim 1, wherein the barrier layer includes nickel, and the second redistribution conductor includes copper.
4. The semiconductor package of claim 1, wherein the encapsulant includes an insulating material including an inorganic filler.
5. The semiconductor package of claim 1, wherein the barrier layer is not in contact with the connection conductor.
8. The semiconductor package of claim 7, wherein the surface metal layer includes nickel.
11. The semiconductor package of claim 10, wherein the seed layer is separated from an upper surface of the encapsulant by the barrier layer.
13. The semiconductor package of claim 10, wherein each of the seed layer and the plating layer includes copper, and the barrier layer includes nickel.
14. The semiconductor package of claim 10, wherein a thickness of the seed layer is about 1 μm or less.
15. The semiconductor package of claim 9, wherein the barrier layer has a thickness of about 1 μm or less.
16. The semiconductor package of claim 9, wherein a side surface of the barrier layer has a step difference with respect to a side surface of the pattern portion.
19. The semiconductor package of claim 18, wherein the second seed layer has a thickness less than a thickness of the first seed layer.
20. The semiconductor package of claim 18, wherein a combination of the barrier layer and the second seed layer has a thickness of about 0.6 μm or less.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
March 29, 2022
November 26, 2024
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