A Thermal Interface Material (TIM) for chip warpage may be provided. A system may comprise an Integrated Circuit (IC) chip, a Thermal Interface Material (TIM) layer disposed on the IC chip, and a heatsink disposed on the TIM layer. The heatsink may comprise, a plate, a plurality of fins, and at least one TIM storage chamber disposed in the plate between two of the plurality of fins. The at least one TIM storage chamber may be filled with a TIM that is solid at a lower temperature end of a thermal cycle of the IC chip and that is liquid at a higher temperature end of the thermal cycle of the IC chip.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The system of claim 1, wherein the first opening is larger than the second opening.
3. The system of claim 1, wherein the at least one TIM storage chamber comprises a conical frustum.
4. The system of claim 1, wherein the at least one TIM storage chamber is positioned over an expected void in the TIM layer.
5. The system of claim 1, wherein the TIM comprises a Phase Change Material (PCM).
6. The system of claim 1, wherein the lower temperature end of the thermal cycle comprises a lower temperature range between 20 degrees Celsius and 40 degrees Celsius inclusively and the higher temperature end of the thermal cycle comprises a higher temperature range between 100 degrees Celsius and 125 degrees Celsius inclusively.
7. The system of claim 1, wherein the plate comprises a vapor chamber.
8. The system of claim 7, wherein the at least one TIM storage chamber is located in a column of the vapor chamber.
9. The system of claim 1, wherein the plate comprises heat pipes.
10. The system of claim 9, wherein the at least one TIM storage chamber is located between the heat pipes.
11. The system of claim 1, wherein the at least one TIM storage chamber is filled with enough TIM material to fill voids in the TIM layer multiple times.
12. The system of claim 1, wherein the IC chip comprises an Application Specific Integrated Circuit (ASIC).
14. The system of claim 13, wherein the lower temperature end of the thermal cycle comprises a lower temperature range between 20 degrees Celsius and 40 degrees Celsius inclusively and the higher temperature end of the thermal cycle comprises a higher temperature range between 100 degrees Celsius and 125 degrees Celsius inclusively.
15. The system of claim 13, wherein the plurality of TIM storage chambers are filled with enough TIM material to fill voids in the TIM layer multiple times.
16. The system of claim 13, wherein the TIM comprises a Phase Change Material (PCM).
18. The method of claim 17, wherein the lower temperature end of the thermal cycle comprises a lower temperature range between 20 degrees Celsius and 40 degrees Celsius inclusively and the higher temperature end of the thermal cycle comprises a higher temperature range between 100 degrees Celsius and 125 degrees Celsius inclusively.
19. The method of claim 17, wherein the TIM storage chamber is positioned over where the void is expected in the TIM layer.
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July 28, 2023
November 26, 2024
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