Patentable/Patents/US-12159922
US-12159922

Method of fabricating semiconductor device

PublishedDecember 3, 2024
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

A method includes forming a dummy gate over a substrate. A first gate spacer is formed on a sidewall of the dummy gate. The dummy gate is replaced with a gate structure. A top portion of the first spacer is removed. After the top portion of the first spacer is removed, a second spacer is over the first spacer. The second spacer has a stepped bottom surface with an upper step in contact with a top surface of the first spacer and a lower step lower than the top surface of the first spacer. A contact plug is formed contacting the gate structure and the second spacer.

Patent Claims
13 claims

Legal claims defining the scope of protection, as filed with the USPTO.

2

2. The method of claim 1, further comprising forming a dielectric cap over the gate structure after forming the second spacer.

3

3. The method of claim 2, wherein the dielectric cap is in contact with the second spacer.

4

4. The method of claim 2, wherein after forming the dielectric cap, a top surface of the dielectric cap is substantially coplanar with a top surface of the second spacer.

5

5. The method of claim 2, wherein the contact plug is further in contact with the dielectric cap.

7

7. The method of claim 6, wherein the first spacer is made of a non-porous material.

8

8. The method of claim 6, wherein the second spacer comprises high-k dielectric materials or non-porous low-k materials.

10

10. The method of claim 9, wherein the dielectric cap over the conductive material is in contact with the sidewall of the second spacer.

14

14. The method of claim 12, wherein the top surface of the first spacer is higher than a top surface of the gate structure.

15

15. The method of claim 12, wherein the second spacer is in contact with the gate structure.

16

16. The method of claim 12, wherein the workpiece further has an air gap between the first spacer and the gate structure.

17

17. The method of claim 1, wherein an air gap is formed between the lower step of the second spacer and a top surface of the substrate.

19

19. The method of claim 1, wherein removing the third spacer comprises removing a top portion of the third spacer when removing the top portion of the first spacer.

20

20. The method of claim 19, wherein after removing the top portion of the third spacer and prior to forming the second spacer, an entirety of the third spacer is removed.

Classification Codes (CPC)

Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.

Patent Metadata

Filing Date

April 17, 2023

Publication Date

December 3, 2024

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Cite as: Patentable. “Method of fabricating semiconductor device” (US-12159922). https://patentable.app/patents/US-12159922

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