A display panel (11) with a low signal transmission power and large cabling space, and a semiconductor display apparatus including the display panel (11) are provided. The display panel (11) includes pixel areas (DB) that are of N rows and M columns and that are connected in a matrix, each pixel area (DB) includes pixel drive modules that are of Q rows and P columns and that are connected in a matrix, each pixel drive circuit (PD) is connected to at least one pixel unit (P), and the pixel drive circuit (PD) drives, based on to-be-displayed image data, the pixel unit (P) to emit light to display an image. All pixel areas (DB) in any column of the pixel areas (DB) are connected to data interfaces (DI) in a same group, and pixel areas (DB) in different columns are connected to data interfaces (DI) in different groups.
Legal claims defining the scope of protection, as filed with the USPTO.
3. The display panel according to claim 2, wherein the data clock signal comprises Q consecutive pulse signals, one-bit image data is loaded to a one-level pixel drive circuit for each pulse signal, and the image data is separately loaded to the Q levels of the pixel drive circuits based on the Q consecutive pulse signals.
6. The display panel according to claim 2, wherein different display driver modules of each pixel area of the first matrix are connected to different clock interfaces, and the display driver circuit comprises P×M data interfaces, M×N data clock interfaces, and M×N global clock interfaces.
8. The display panel according to claim 7, wherein each pixel drive circuit is connected to four pixel units of the at least one pixel units, the each pixel drive circuit comprises one input interface and four groups of output interfaces, the one input interface is connected to the one data interface, and one group of the output interfaces is connected to cathodes of the three light emitting elements in one pixel unit.
9. The display panel according to claim 8, wherein the each pixel drive circuit is a micro integrated circuit.
12. The semiconductor display apparatus according to claim 11, wherein the data clock signal comprises Q consecutive pulse signals, one-bit image data is loaded to a one-level pixel drive circuit for each pulse signal, and the image data is separately loaded to the Q levels of the pixel drive circuits based on the Q consecutive pulse signals.
15. The semiconductor display apparatus according to claim 11, wherein different display driver modules of each pixel area of the first matrix are connected to different clock interfaces, and the display driver circuit comprises P×M data interfaces, M×N data clock interfaces, and M×N global clock interfaces.
17. The semiconductor display apparatus according to claim 16, wherein each pixel drive circuit is connected to four pixel units of the at least one pixel units, the each pixel drive circuit comprises one input interface and four groups of output interfaces, the one input interface is connected to the one data interface, and one group of the output interfaces is connected to cathodes of the three light emitting elements in one pixel unit.
18. The semiconductor display apparatus panel according to claim 17, wherein the each pixel drive circuit is a micro integrated circuit.
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March 20, 2023
December 10, 2024
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