A method includes: providing a modulation circuit including a first resistive element, a second resistive element and a third resistive element; providing a memory array and a regulator connecting the modulation circuit to the memory array, wherein the regulator includes a transistor; determining an operation mode of the memory array; generating a first voltage at a drain terminal of the transistor, wherein the first voltage corresponds to a positive, negative zero temperature coefficient according to a first resistance ratio and a second resistance ratio; during a read operation, providing a first driving current to the memory array in response to the first voltage corresponding to the positive temperature coefficient; and during a write operation, providing a second driving current to the memory array in response to the first voltage corresponding to the negative temperature coefficient.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The method of claim 1, wherein the regulator further comprises a comparator and a voltage divider, wherein the voltage divider comprises a tap connected to a first input terminal of the comparator, where the comparator further comprises a second input terminal configured to receive an output voltage of the modulation circuit.
3. The method of claim 2, wherein the voltage divider is connected to the drain terminal of the transistor.
4. The method of claim 3, wherein the memory array comprises a word line driver configured to receive the first voltage of the regulator.
5. The method of claim 4, wherein each of the first resistive element, the second resistive element and the third resistive element is a variable resistive element comprising a plurality of resistive elements and a plurality of switches connected to the resistive elements.
6. The method of claim 5, wherein the modulation circuit comprises three transistors having their gates connected together and having their drains connected to the first resistive element, the second resistive element, and the third resistive element, respectively.
8. The method of claim 7, wherein the output current is provided to a word line of the memory array.
9. The method of claim 7, wherein the memory array further comprises a word line driver configured to generate the output current according to the first voltage or the second voltage to enable the read operation or the write operation.
10. The method of claim 7, wherein the regulator comprises a first comparator, a transistor and a voltage divider, wherein the transistor includes a gate connected to a first input terminal of the first comparator and a drain connected to the voltage divider.
11. The method of claim 10, wherein the first comparator further comprises a second input terminal connected to the modulation circuit.
12. The method of claim 7, wherein the modulation circuit further comprises a first transistor, a second transistor and a third transistor each including a drain connected to the first adjustable resistive element, the second adjustable resistive element and the third adjustable resistive element, respectively.
13. The method of claim 12, wherein the drain of the first transistor is configured to provide the first voltage or the second voltage, and the drains of the second transistor and the third transistor are connected to two input terminals of a second comparator of the modulation circuit.
14. The method of claim 13, wherein the first transistor, the second transistor and the third transistor of the modulation circuit having gates connected together.
15. The method of claim 14, wherein the gates of the second transistor and the third transistor of the modulation circuit are connected to an output terminal of the second comparator.
16. The method of claim 12, wherein the first transistor, the second transistor and the third transistor of the modulation circuit having gates connected together.
18. The method of claim 17, wherein the first branch current of the first current is corresponding to the positive temperature coefficient.
19. The method of claim 17, wherein the second branch current of the first current is corresponding to the negative temperature coefficient.
20. The method of claim 17, wherein the first branch current of the second current is corresponding to the positive temperature coefficient.
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July 30, 2023
December 10, 2024
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