Methods, systems, and devices for status check using chip enable pin are described. An apparatus may include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first a voltage or a second voltage based on a status of the memory device. The status may indicate, for example, whether the memory device is available to receive a command. The driver may bias the pin to a first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally, or alternatively, the driver may bias the pin to a second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin may be an example of a chip enable pin.
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2. The memory system of claim 1, wherein the first voltage is lower than the second voltage.
4. The memory system of claim 1, wherein the one or more controllers are configured to cause the memory system to bias the pin to the first voltage and the second voltage based at least in part on a resistance of the one or more drivers.
7. The memory system of claim 1, wherein the second voltage satisfies a threshold voltage that indicates that the one or more memory devices are inaccessible.
9. The method of claim 8, wherein the first voltage is lower than the second voltage.
11. The method of claim 8, wherein biasing the pin to the first voltage and the second voltage is based at least in part on a resistance of one or more drivers coupled with the one or more memory devices.
14. The method of claim 8, wherein the second voltage satisfies a threshold voltage that indicates that the one or more memory devices are inaccessible.
16. The non-transitory computer-readable medium of claim 15, wherein the first voltage is lower than the second voltage.
18. The non-transitory computer-readable medium of claim 15, wherein the instructions are further executable by the one or more processors to bias the pin to the first voltage and the second voltage based at least in part on a resistance of one or more drivers coupled with the one or more memory devices.
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October 11, 2022
December 17, 2024
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