A processor comprises a computational array of computational elements and an instruction dispatch circuit. The computational elements receive data operands via data lanes extending along a first dimension, and processes the operands based upon instructions received from the instruction dispatch circuit via instruction lanes extending along a second dimension. The instruction dispatch circuit receives raw instructions, and comprises an instruction dispatch unit (IDU) processor that processes a set of raw instructions to generate processed instructions for dispatch to the computational elements, where the number of processed instructions is not equal to the number of instructions of the set of raw instructions. The processed instructions are dispatched to columns of the computational array via a plurality of instruction queues, wherein an instruction vector of instructions is shifted between adjacent instruction queues in a first direction, and dispatches instructions to the computational elements in a second direction.
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2. The processor of claim 1, wherein the computational elements are homogeneous.
3. The processor of claim 1, wherein the computational elements are heterogeneous.
4. The processor of claim 1, wherein the arrangement of computational elements is an array, the data flow in the first direction is along rows of the array, and instruction control is applied to columns of the array.
5. The processor of claim 1, wherein the instructions move only in a row direction during certain timing increments.
6. The processor of claim 1, wherein the instructions move only in a column direction during certain timing increments.
7. The processor of claim 1, wherein the instruction dispatch circuit is configured to dispatch instructions to columns of computational elements in a Single Instruction Multiple Data (SIMD) configuration.
8. The processor of claim 1, wherein the instruction dispatch circuit is configured to dispatch instructions to columns of computational elements in a Multiple Instructions Multiple Data (MIMD) configuration.
10. The method of claim 9, wherein the arrangement of computational elements is configured to process data operands provided from memory based upon the provided instructions.
11. The method of claim 9, wherein the computational elements are homogeneous.
12. The method of claim 9, wherein the computational elements are heterogeneous.
13. The method of claim 9, wherein the arrangement of computational elements is an array, the data flow in the first direction is along rows of the array, and instruction control is applied to columns of the array.
14. The method of claim 9, wherein the instructions move only in a row direction during certain timing increments.
15. The method of claim 9, wherein the instructions may move only in a column direction during certain timing increments.
16. The method of claim 9, wherein the providing instructions comprises dispatching instructions to columns of computational elements in a Single Instruction Multiple Data (SIMD) configuration.
17. The method of claim 9, wherein the providing instructions comprises dispatching instructions to columns of computational elements in a Multiple Instructions Multiple Data (MIMD) configuration.
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December 20, 2023
December 24, 2024
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