A multiple pixel package structure with a buried chip and an electronic device using the same are provided. The multiple pixel package structure includes a multi-layered circuit board, a plurality of pixels, a protective layer, and a control chip. The pixels are arranged on the multi-layered circuit board and into an array. Each of the pixels includes a plurality of light emitting elements of different colors. The protective layer is formed on the multi-layered circuit board and covers the pixels. The control chip is buried in the multi-layered circuit board and electrically connected to the light emitting elements of each of the pixels, so as to allow each of the pixels to produce a target luminous characteristic.
Legal claims defining the scope of protection, as filed with the USPTO.
2. The multiple pixel package structure according to claim 1, wherein the annular space has a width between 10 μm and 100 μm.
3. The multiple pixel package structure according to claim 2, wherein a thickness of the base layer is 0 μm to 20 μm less than a height of the control chip.
4. The multiple pixel package structure according to claim 2, wherein the control chip has an active surface that is perpendicular to the outer peripheral surface and is in proximity to the first surface of the base layer, and the active surface has a plurality of electrical contacts; and wherein the number of the light emitting elements of each of the pixels is L, and the number of the electrical contacts is M×N×L.
5. The multiple pixel package structure according to claim 4, wherein the multi-layered circuit board includes a plurality of connecting pads at a bottom thereof, and the number of the connecting pads is less than M×N×L.
6. The multiple pixel package structure according to claim 1, wherein the multi-layered circuit board further includes another upper patterned metal layer laminated on the upper patterned metal layer and another lower patterned metal layer laminated on the lower patterned metal layer, the control chip is electrically connected to the another upper patterned metal layer through the upper patterned metal layer and is electrically connected to the another lower patterned metal layer through the lower patterned metal layer; and wherein the pixels are disposed on the another upper patterned metal layer.
7. The multiple pixel package structure according to claim 6, wherein the control chip has an active surface that is in proximity to the first surface of the base layer and has a plurality of electrical contacts; wherein each of the upper patterned metal layer and the another upper patterned metal layer includes an inside circuit and an outside circuit around the inside circuit, and the light emitting elements of each of the pixels are electrically connected to the inside circuit of the another upper patterned metal layer and are electrically connected to the corresponding ones of the plurality of electrical contacts via the inside circuit of the other upper patterned metal layer; and wherein the another lower patterned metal layer defines a plurality of connecting pads, the lower patterned metal layer includes an outside circuit, a portion of the plurality of the connecting pads are electrically connected to a portion of the plurality of electrical contacts via the outside circuit of the lower patterned metal layer, and another portion of the plurality of the connecting pads are electrically connected to another portion of the plurality of electrical contacts via the outside circuit of the lower patterned metal layer and the outside circuits of the upper patterned metal layer and the another upper patterned metal layer.
8. The multiple pixel package structure according to claim 1, wherein the gap filling layer is integrated with the adhesive layer and the another adhesive layer.
9. The multiple pixel package structure according to claim 1, wherein an upper insulating core layer is formed between the upper patterned metal layer and the another upper patterned metal layer, and has a plurality of upper conductive vias for connecting the upper patterned metal layer and the another upper patterned metal layer; and wherein a lower insulating core layer is formed between the lower patterned metal layer and the another lower patterned metal layer, and has a plurality of lower conductive vias for connecting the lower patterned metal layer and the another lower patterned metal layer.
10. An electronic device characterized by using the multiple pixel package structure as claimed in claim 1.
11. The multiple pixel package structure according to claim 1, wherein each of the pixels includes a plurality of light emitting elements of different colors.
12. The multiple pixel package structure according to claim 1, further comprising a protective layer formed on the multi-layered circuit board and covering the pixels.
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May 18, 2021
December 31, 2024
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