A semiconductor device structure, along with methods of forming such, are described. The structure includes a first, second, and third gate electrode layers, a first dielectric feature disposed between the first and second gate electrode layers, a second dielectric feature disposed between the second and third gate electrode layers, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer.
Legal claims defining the scope of protection, as filed with the USPTO.
7. The method of claim 1, wherein the forming the first dielectric material in the first opening comprises forming the first dielectric material on the conductive layer.
10. The method of claim 9, further comprising a contact etch stop layer formed on the two ILD layers.
11. The method of claim 10, further comprising spacers disposed adjacent and in contact with the contact etch stop layer, wherein the portion of the seed layer disposed adjacent the two ILD layers is in contact with the spacers.
12. The method of claim 11, further comprising a nitrogen-containing layer disposed on each of the two ILD layers, wherein the portion of the seed layer disposed over the two ILD layers is disposed on the nitrogen-containing layer.
13. The method of claim 9, further comprising forming an opening in the conductive layer and the seed layer.
14. The method of claim 13, wherein the opening is formed by a first etch process to remove a portion of the conductive layer and a second etch process to remove a portion of the seed layer.
16. The method of claim 15, further comprising performing a first etch process to form an opening in the conductive layer, wherein a portion of the seed layer is exposed in the opening.
17. The method of claim 16, further comprising performing a second etch process to remove the exposed portion of the seed layer and to expose the dielectric feature.
18. The method of claim 17, further comprising depositing a dielectric material in the opening and on the conductive layer, wherein the dielectric material is in contact with the dielectric feature.
19. The method of claim 18, wherein the seed layer and the conductive layer are deposited in a trench, and the dielectric material fills the trench.
20. The method of claim 19, wherein the trench is formed between two interlayer dielectric layers.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 23, 2023
December 31, 2024
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