In a control circuit for a switching stage of an electronic converter, a phase detector generates a drive signal in response to a phase difference between first and second clock signals. The first and second clock signals are generated by first and second current-controlled oscillators, respectively. An operational transconductance amplifier generates first and second control currents in response to a difference between a reference and a feedback of the electronic converter, with the first and second currents applied to control the first and second current-controlled oscillators. In response to a switching clock having a first state, a switching circuit applies first and second bias currents to the control inputs of the first and second current-controlled oscillators, respectively. Conversely, in response to the switching clock having a second state, the switching circuit applies the second and first bias currents to the control inputs of the first and second current-controlled oscillators, respectively.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A control circuit for a switching stage of an electronic converter configured to provide an output voltage, the control circuit comprising: a first terminal configured to provide a drive signal to a corresponding electronic switch of said switching stage; a second terminal configured to receive a first feedback signal proportional to said output voltage from a feedback circuit; a driver circuit configured to generate said drive signal as a function of a Pulse-Width Modulation (PWM) signal; and a PWM signal generator circuit configured to generate said PWM signal as a function of said first feedback signal and a reference voltage, wherein said PWM signal generator circuit comprises: a first current-controlled oscillator having an input terminal configured to receive a first current and generate a first clock signal as a function of said first current; a second current-controlled oscillator having an input terminal configured to receive a second current and generate a second clock signal as a function of said second current; a first operational transconductance amplifier configured to provide at a first amplifier output a third current indicative of a difference between said reference voltage and said first feedback signal, wherein said first amplifier output of said first operational transconductance amplifier is connected to said input terminal of said first current-controlled oscillator; and a phase detector having inputs coupled to said first oscillator and said second oscillator and providing at an output said PWM signal; wherein said PWM signal generator circuit further comprises: a first bias current generator configured to provide a first bias current at a first bias output; a second bias current generator configured to provide a second bias current at a second bias output; and a switching circuit configured to receive a switch clock signal and: when a logic level of said switch clock signal has a first logic level, connect the first bias output of said first bias current generator to the input terminal of said first current-controlled oscillator and connect the second bias output of said second bias current generator to the input terminal of said second current-controlled oscillator, and when the logic level of said switch clock signal has a second logic level, connect the first bias output of said first bias current generator to the input terminal of said second current-controlled oscillator and connect the second bias output of said second bias current generator to the input terminal of said first current-controlled oscillator.
2. The control circuit according to claim 1, wherein said switch clock signal is derived from said first clock signal or said second clock signal.
3. The control circuit according to claim 2, wherein said switch clock signal corresponds to one of said first clock signal or said second clock signal.
4. The control circuit according to claim 1, wherein said PWM signal generator circuit further comprises: a first delay line connected between said first current-controlled oscillator and said phase detector, and a second delay line connected between said second current-controlled oscillator and said phase detector.
5. The control circuit according to claim 4, wherein one or more of said first delay line and second delay line is driven as a function of the difference between said reference voltage and said first feedback signal.
6. The control circuit according to claim 4, comprising a terminal configured to receive from an analog differentiator a second feedback signal proportional to a derivative of said output voltage, and wherein one or more of said first delay line and second delay line is driven as a function of the difference between said reference voltage and said second feedback signal.
7. The control circuit according to claim 6, comprising at least one of: said one or more electronic switches of said switching stage; said feedback circuit; and said analog differentiator.
8. The control circuit according to claim 6, wherein each of said first delay line and said second delay line is a current-controlled delay line, and wherein said PWM signal generator circuit further comprises: a second operational transconductance amplifier configured to generate a fourth current indicative of a difference between said reference voltage and said first feedback signal; a third operational transconductance amplifier configured to generate a fifth current indicative of a difference between said reference voltage and said second feedback signal; wherein said fourth current and said fifth current are provided to one or more of the first delay line and the second delay line.
9. The control circuit according to claim 1, wherein said first operational transconductance amplifier is a differential operational transconductance amplifier configured to provide at a second amplifier output a sixth current, wherein a difference between said sixth current and said third current is proportional to a difference between a reference voltage and said first feedback signal, and wherein said second amplifier output of said first operational transconductance amplifier is connected to said input terminal of said second current-controlled oscillator.
10. The control circuit according to claim 1, wherein said electronic converter is a buck or boost converter.
11. The control circuit according to claim 1, where a frequency of the switch clock signal is outside a bandwidth of a control loop for the control circuit.
12. An integrated circuit comprising a control circuit according to claim 1.
13. An electronic converter, comprising: a switching stage, and a control circuit according to claim 1.
14. A control circuit for a switching stage of an electronic converter configured to generate an output voltage, comprising: a feedback circuit configured to generate a feedback signal from said output voltage; an operational transconductance amplifier configured to generate, in response to a difference between a reference voltage and said feedback signal, a first output current and a second output current; a first current-controlled oscillator having an input coupled to receive the first output current and configured to generate a first clock signal; a second current-controlled oscillator having an input coupled to receive the second output current and configured to generate a second clock signal; a phase detector circuit configured to generate a drive signal for the switching stage of the electronic converter in response to a phase difference between the first and second clock signals; a first bias current generator configured to generate a first bias current; a second bias current generator configured to generate a second bias current; and a switching circuit controlled by a switch clock signal to: when the switch clock signal has a first logic level, apply the first bias current to the input of said first current-controlled oscillator and apply the second bias current to the input of the said second current-controlled oscillator, and when the switch clock signal has a second logic level, apply the second bias current to the input of said first current-controlled oscillator and apply the first bias current to the input of the said second current-controlled oscillator.
15. The control circuit according to claim 14, wherein a frequency of the switch clock signal is outside a bandwidth of a control loop for the control circuit.
16. The control circuit according to claim 14, wherein said switch clock signal is derived from said first clock signal.
17. The control circuit according to claim 14, wherein said switch clock signal is derived from said second clock signal.
18. The control circuit according to claim 14, wherein said switch clock signal corresponds to said first clock signal.
19. The control circuit according to claim 14, wherein said switch clock signal corresponds to said second clock signal.
20. The control circuit according to claim 14, wherein said electronic converter is a buck or boost converter.
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November 8, 2022
January 7, 2025
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