Embodiments may relate to a microelectronic package that includes a die coupled with a package substrate. A plurality of solder thermal interface material (STIM) thermal interconnects may be coupled with the die and an integrated heat spreader (IHS) may be coupled with the plurality of STIM thermal interconnects. A thermal underfill material may be positioned between the IHS and the die such that the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects. Other embodiments may be described or claimed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A microelectronic package, comprising: a package substrate; a die coupled with the package substrate at a first face of the die; a plurality of solder thermal interface material (STIM) thermal interconnects coupled with the die at a second face of the die, wherein the second face is opposite the first face; an integrated heat spreader (IHS) coupled with the plurality of STIM thermal interconnects, wherein a first STIM thermal interconnect of the plurality of STIM thermal interconnects has a different size or shape than a second STIM thermal interconnect of the plurality of STIM thermal interconnects; and a thermal underfill material positioned between the IHS and the die, wherein the thermal underfill material at least partially surrounds the plurality of STIM thermal interconnects.
2. The microelectronic package of claim 1, further comprising a patterning layer positioned between a STIM thermal interconnect of the plurality of STIM thermal interconnects and the IHS.
3. The microelectronic package of claim 1, further comprising a solder resist layer coupled to the second face of the die and adjacent to, and at least partially surrounding, a STIM thermal interconnect of the plurality of STIM thermal interconnects.
4. The microelectronic package of claim 1, further comprising a solder resist layer coupled to the IHS and adjacent to, and at least partially surrounding, a STIM thermal interconnect of the plurality of STIM thermal interconnects.
5. The microelectronic package of claim 1, wherein the plurality of STIM thermal interconnects is coupled with the second face of the die in a randomized pattern.
6. The microelectronic package of claim 1, wherein the plurality of STIM thermal interconnects is coupled with the second face of the die in a grid pattern.
7. The microelectronic package of claim 1, wherein a distance between the second face of the die and the IHS is less than 150 micrometers.
8. A microelectronic package comprising: a die coupled with a package substrate; a plurality of solder thermal interface material (STIM) thermal interconnects coupled with a face of the die, wherein the plurality of STIM thermal interconnects is at least partially surrounded by a thermal underfill material and has a height of less than 50 micrometers; an integrated heat spreader (IHS) coupled with the plurality of STIM thermal interconnects, wherein the die is between the IHS and the package substrate; and a spacer that is physically coupled with the IHS and the package substrate.
9. The microelectronic package of claim 8, further comprising a patterning layer between the IHS and an STIM thermal interconnect of the plurality of STIM thermal interconnects.
10. The microelectronic package of claim 8, further comprising a solder resist layer adjacent to an STIM thermal interconnect of the plurality of STIM thermal interconnects and coupled to the face of the die or the IHS.
11. The microelectronic package of claim 8, wherein the spacer includes steel, copper, aluminum, or polymer.
12. The microelectronic package of claim 8, wherein the spacer is a first spacer and wherein the microelectronic package further comprises a second spacer that is adjacent to the first spacer, and wherein the second spacer is physically coupled with the IHS and the package substrate.
13. The microelectronic package of claim 8, wherein the spacer is a solder ball.
14. The microelectronic package of claim 8, wherein the spacer is coupled with the package substrate or the IHS by an adhesive material or by a further STIM thermal interconnect.
15. A microelectronic package, comprising: a die coupled with a package substrate; a plurality of solder thermal interface material (STIM) thermal interconnects coupled with a face of the die, wherein the plurality of STIM thermal interconnects is at least partially surrounded by a thermal underfill material; and an integrated heat spreader (IHS) coupled with the package substrate and the plurality of STIM thermal interconnects, wherein the die is between the IHS and the package substrate, wherein the IHS includes a leg portion coupled with the package substrate.
16. The microelectronic package of claim 15, wherein the leg portion is coupled with the package substrate by an adhesive material or by a further STIM thermal interconnect.
17. The microelectronic package of claim 15, wherein the die is a first die, the plurality of STIM thermal interconnects is a first plurality of STIM thermal interconnects, the thermal underfill material is a first thermal underfill material, and the microelectronic package further includes: a second die coupled with the package substrate; a second plurality of STIM thermal interconnects between the second die and the IHS; and a second thermal underfill material between the IHS and the second die, wherein the second thermal underfill material at least partially surrounds the second plurality of STIM thermal interconnects.
18. The microelectronic package of claim 17, wherein the second plurality of STIM thermal interconnects has a different height as measured in a direction perpendicular to a face of the second die to which they are coupled as a height of the first plurality of STIM thermal interconnects.
19. The microelectronic package of claim 15, wherein a height of the plurality of STIM thermal interconnects is less than 150 micrometers.
20. The microelectronic package of claim 15, wherein the plurality of STIM thermal interconnects is coupled with the face of the die in a two-dimensional array pattern.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
July 3, 2023
January 21, 2025
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.