Apparatuses, devices and systems associated with semiconductor packages with chiplet and memory device coupling are disclosed herein. In embodiments, a semiconductor package may include a first chiplet, a second chiplet, and a memory device. The semiconductor package may further include an interconnect structure that couples the first chiplet to a first memory channel of the memory device and the second chiplet to a second memory channel of the memory device. Other embodiments may be described and/or claimed.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A package comprising: a package substrate; a device above the package substrate, the device having a first edge, a second edge, a third edge, and a fourth edge, the first edge laterally opposite the third edge, and the second edge laterally opposite the fourth edge; a first die above the package substrate, the first die laterally spaced apart from the first edge of the device; a first bridge in the package substrate beneath the first die and the device, the first bridge coupling the first die to the device; a second die above the package substrate, the second die laterally spaced apart from the first edge of the device; a second bridge in the package substrate beneath the second die and the device, the second bridge coupling the second die to the device; a third die above the package substrate, the third die laterally spaced apart from the third edge of the device; a third bridge in the package substrate beneath the third die and the device, the third bridge coupling the third die to the device; a fourth die above the package substrate, the fourth die laterally spaced apart from the third edge of the device; a fourth bridge in the package substrate beneath the fourth die and the device, the fourth bridge coupling the fourth die to the device; and a plurality of conductive vias in the package substrate, a first group of the plurality of conductive vias laterally spaced apart from a first side of the first bridge, a second group of the plurality of conductive vias laterally between a second side of the first bridge and a first side of the second bridge, and a third group of the plurality of conductive vias laterally spaced apart from a second side of the second bridge.
2. The package of claim 1, wherein no die are coupled to the second side of the device.
3. The package of claim 2, wherein no die are coupled to the fourth side of the device.
4. The package of claim 1, wherein the first die comprises a first memory controller, the second die comprises a second memory controller, the third die comprises a third memory controller, and the fourth die comprises a fourth memory controller.
5. The package of claim 4, wherein the first memory controller is coupled to a first memory channel of the device, the second memory controller is coupled to a second memory channel of the device, the third memory controller is coupled to a third memory channel of the device, and the fourth memory controller is coupled to a fourth memory channel of the device.
6. The package of claim 1, wherein the device is a memory device.
7. The package of claim 1, wherein the first die is a first chiplet, the second die is a second chiplet, the third die is a third chiplet, and the fourth die is a fourth chiplet.
8. The package of claim 7, wherein the first chiplet, the second chiplet, the third chiplet, and the fourth chiplet form an electronic component.
9. The package of claim 1, wherein the first die is coupled to the first bridge and to the package substrate by a first plurality of interconnect elements, the second die is coupled to the second bridge and to the package substrate by a second plurality of interconnect elements, the third die is coupled to the third bridge and to the package substrate by a third plurality of interconnect elements, and the fourth die is coupled to the fourth bridge and to the package substrate by a fourth plurality of interconnect elements.
10. The package of claim 1, wherein the first bridge is embedded in the package substrate, the second bridge is embedded in the package substrate, the third bridge is embedded in the package substrate, and the fourth bridge is embedded in the package substrate.
11. A system, comprising: a printed circuit board (PCB); and a package coupled to the printed circuit board, the package substrate comprising: a package substrate; a device above the package substrate, the device having a first edge, a second edge, a third edge, and a fourth edge, the first edge laterally opposite the third edge, and the second edge laterally opposite the fourth edge; a first die above the package substrate, the first die laterally spaced apart from the first edge of the device; a first bridge in the package substrate beneath the first die and the device, the first bridge coupling the first die to the device; a second die above the package substrate, the second die laterally spaced apart from the first edge of the device; a second bridge in the package substrate beneath the second die and the device, the second bridge coupling the second die to the device; a third die above the package substrate, the third die laterally spaced apart from the third edge of the device; a third bridge in the package substrate beneath the third die and the device, the third bridge coupling the third die to the device; a fourth die above the package substrate, the fourth die laterally spaced apart from the third edge of the device; a fourth bridge in the package substrate beneath the fourth die and the device, the fourth bridge coupling the fourth die to the device; and a plurality of conductive vias in the package substrate, a first group of the plurality of conductive vias laterally spaced apart from a first side of the first bridge, a second group of the plurality of conductive vias laterally between a second side of the first bridge and a first side of the second bridge, and a third group of the plurality of conductive vias laterally spaced apart from a second side of the second bridge.
12. The system of claim 11, wherein no die are coupled to the second side of the device.
13. The system of claim 12, wherein no die are coupled to the fourth side of the device.
14. The system of claim 11, wherein the first die comprises a first memory controller, the second die comprises a second memory controller, the third die comprises a third memory controller, and the fourth die comprises a fourth memory controller.
15. The system of claim 14, wherein the first memory controller is coupled to a first memory channel of the device, the second memory controller is coupled to a second memory channel of the device, the third memory controller is coupled to a third memory channel of the device, and the fourth memory controller is coupled to a fourth memory channel of the device.
16. The system of claim 11, wherein the device is a memory device.
17. The system of claim 11, wherein the first die is a first chiplet, the second die is a second chiplet, the third die is a third chiplet, and the fourth die is a fourth chiplet.
18. The system of claim 17, wherein the first chiplet, the second chiplet, the third chiplet, and the fourth chiplet form an electronic component.
19. The system of claim 11, wherein the first die is coupled to the first bridge and to the package substrate by a first plurality of interconnect elements, the second die is coupled to the second bridge and to the package substrate by a second plurality of interconnect elements, the third die is coupled to the third bridge and to the package substrate by a third plurality of interconnect elements, and the fourth die is coupled to the fourth bridge and to the package substrate by a fourth plurality of interconnect elements.
20. The system of claim 11, wherein the first bridge is embedded in the package substrate, the second bridge is embedded in the package substrate, the third bridge is embedded in the package substrate, and the fourth bridge is embedded in the package substrate.
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February 21, 2023
January 21, 2025
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