According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device, comprising: a first semiconductor layer; a second semiconductor layer provided on and above the first semiconductor layer; a third semiconductor layer provided on and above the second semiconductor layer; a stacked body provided above the third semiconductor layer, the stacked body including a plurality of electrode layers stacked in a first direction; a columnar portion including a fourth semiconductor layer and a first charge storage film, the fourth semiconductor layer extending through the stacked body, the third semiconductor layer, and the second semiconductor layer, and reaching the first semiconductor layer in the first direction, the fourth semiconductor layer including a side wall portion in contact with the second semiconductor layer; and a separate portion extending through the stacked body and the third semiconductor layer in the first direction, extending in a second direction crossing the first direction, and dividing the stacked body into a first portion and a second portion in a third direction crossing the first direction and the second direction, wherein the separate portion includes a core layer, a first insulating layer between the first portion of the stacked body and the core layer, and a second insulating layer between the second portion of the stacked body and the core layer, and a lower end of the separate portion protrudes lower than a lower surface of the third semiconductor layer.
2. The device according to claim 1, wherein a lower end of the core layer protrudes lower than the lower surface of the third semiconductor layer.
3. The device according to claim 1, wherein the core layer is a conductive layer.
4. The device according to claim 3, wherein the core layer is in contact with the second semiconductor layer.
5. The device according to claim 1, wherein the first charge storage film is provided between the stacked body and the fourth semiconductor layer.
6. The device according to claim 1, wherein the side wall portion of the fourth semiconductor layer is not covered with the first charge storage film.
7. The device according to claim 1, wherein the second semiconductor layer includes an impurity.
8. The device according to claim 1, further comprising a gate layer provided between the third semiconductor layer and the stacked body, the gate layer being thicker than a thickness of one layer of the plurality of electrode layers.
9. The device according to claim 8, wherein a distance between the side wall portion of the fourth semiconductor layer and a portion of the fourth semiconductor layer opposing the gate layer is less than a thickness of the gate layer.
10. The device according to claim 8, wherein an impurity concentration of a first portion of the fourth semiconductor layer opposing the gate layer is higher than an impurity concentration of a second portion of the fourth semiconductor layer opposing the stacked body.
11. The device according to claim 8, wherein at least one of the plurality of electrode layers is a first selection gate, at least one of the plurality of electrode layers except for the first selection gate is a second selection gate, plurality of the plurality of electrode layers except for the first selection gate and the second selection gate are a plurality of cell gates, the first selection gate is thinner than the gate layer, the second selection gate is provided between the first selection gate and the gate layer, and is thinner than the gate layer, and the plurality of cell gates oppose the first charge storage film, and is provided between the first selection gate and the second selection gate, and the plurality of cell gates each are thinner than the gate layer.
12. The device according to claim 8, wherein the gate layer is a silicon layer including phosphorus.
13. The device according to claim 8, wherein the first charge storage film is provided between the gate layer and the fourth semiconductor layer.
14. The device according to claim 8, wherein the device is configured to apply a potential to the gate layer in an erase operation so as to occur holes in a portion of the fourth semiconductor layer opposing the gate layer.
15. The device according to claim 1, wherein an impurity concentration of the side wall portion of the fourth semiconductor layer is higher than an impurity concentration of a portion of the fourth semiconductor layer opposing the stacked body.
16. The device according to claim 1, wherein the first semiconductor layer is a silicon layer including phosphorus.
17. The device according to claim 1, wherein the second semiconductor layer is a silicon layer including phosphorus.
18. The device according to claim 1, wherein the third semiconductor layer is a silicon layer including phosphorus.
19. The device according to claim 1, further comprising a substrate, the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer being provided between the substrate and the stacked body layer, the first semiconductor layer contacting the substrate.
20. The device according to claim 1, further comprising a second charge storage film provided between the first semiconductor layer and the fourth semiconductor layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 10, 2024
January 21, 2025
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