Semiconductor package including a dummy pattern

1. A semiconductor package, comprising: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer including a first hole; a second dielectric layer on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; and a connection member bonded to the under bump.

2. The semiconductor package of claim 1, wherein a sidewall of the under bump has an inflection point.

3. The semiconductor package of claim 1, wherein the first substrate further includes a dummy pattern spaced apart from the under bump, the dummy pattern penetrating the second dielectric layer and contacting the first dielectric layer, wherein a portion of the dummy pattern covers a top surface of the second dielectric layer, and wherein a bottom surface of the dummy pattern is coplanar with a bottom surface of the second dielectric layer.

4. The semiconductor package of claim 3, wherein the dummy pattern is electrically floated or is provided with a ground voltage.

5. The semiconductor package of claim 3, wherein the dummy pattern and the under bump include the same metal, and a top surface of the dummy pattern is at the same height as a top surface of the under bump.

6. The semiconductor package of claim 3, wherein, when viewed in plan, the dummy pattern has a circular shape, a tetragonal shape whose sidewalls are concave, or a mesh shape.

7. The semiconductor package of claim 3, wherein the under bump has a first thickness, and the dummy pattern has a second thickness less than the first thickness.

8. The semiconductor package of claim 3, wherein an interval between the under bump and the dummy pattern is about 5 μm to about 50 μm.

9. The semiconductor package of claim 3, wherein the second dielectric layer includes a dummy hole into which the dummy pattern is inserted, the dummy hole exposing a top surface of the first dielectric layer, wherein the dummy pattern includes: a seed layer that covers an inner sidewall and a bottom surface of the dummy hole; and a dummy metal pattern that fills the dummy hole.

10. The semiconductor package of claim 9, wherein an inner sidewall of the second hole makes a first angle with a bottom surface of the second dielectric layer, the inner sidewall of the dummy hole makes a second angle with the bottom surface of the second dielectric layer, and the first angle is substantially the same as the second angle.

11. The semiconductor package of claim 1, wherein the under bump includes: a barrier/seed pattern that covers at least an inner sidewall of the second hole; and a bump metal pattern disposed on the barrier/seed pattern and filling the second hole and the first hole, and wherein an air gap is provided between the bump metal pattern and an inner sidewall of the first hole.

12. The semiconductor package of claim 11, wherein the connection member is in contact with the bump metal pattern.

13. A semiconductor package, comprising: a package substrate; an interposer substrate on the package substrate; a first semiconductor device and a second semiconductor device mounted side by side on the interposer substrate; and a thermal radiation member that covers the first semiconductor device, the second semiconductor device, the interposer substrate, and the package substrate, wherein the interposer substrate includes: a first dielectric layer including a first hole; a second dielectric layer disposed on the first dielectric layer and including a second hole that overlaps the first hole, the second hole being wider than the first hole; an under bump disposed in the first hole and the second hole, the under bump covering a portion of the second dielectric layer; a connection member bonded to the under bump; and a dummy pattern spaced apart from the under bump, the dummy pattern penetrating the second dielectric layer and contacting the first dielectric layer, wherein a portion of the dummy pattern covers a top surface of the second dielectric layer, wherein a bottom surface of the dummy pattern is coplanar with a bottom surface of the second dielectric layer, and wherein an interval between the under bump and the dummy pattern is about 5 μm to about 50 μm.

14. The semiconductor package of claim 13, wherein the dummy pattern is electrically floated or is provided with a ground voltage.

15. The semiconductor package of claim 13, wherein the dummy pattern and the under bump include the same metal, and a top surface of the dummy pattern is at the same height as a top surface of the under bump.

16. The semiconductor package of claim 13, wherein, when viewed in plan, the dummy pattern has a circular shape, a tetragonal shape whose sidewalls are concave, or a mesh shape.

17. A semiconductor package, comprising: a first substrate and a semiconductor device on the first substrate, wherein the first substrate includes: a first dielectric layer; an under bump and a dummy pattern that are in the first dielectric layer and are spaced apart from each other; and a connection member in contact with a bottom surface of the under bump, wherein each of the under bump and the dummy pattern includes: a first part inserted into the first dielectric layer; and a second part that protrudes beyond the first dielectric layer and covers a top surface of the first dielectric layer, wherein a sidewall of the first part of the under bump has an inflection point, and wherein a bottom surface of the dummy pattern is covered with a portion of the first dielectric layer.

18. The semiconductor package of claim 17, wherein a length of a sidewall of the under bump is greater than a length of a sidewall of the dummy pattern.

19. The semiconductor package of claim 17, wherein the under bump includes: a barrier/seed pattern in contact with the first dielectric layer; and a bump metal pattern on the barrier/seed pattern and in contact with the connection member, wherein an air gap is between the connection member and the barrier/seed pattern.

20. The semiconductor package of claim 17, wherein, when viewed in plan, the dummy pattern has a circular shape, a tetragonal shape whose sidewalls are concave, or a mesh shape.