A memory device includes a command interface configured to receive write commands from a host device. The memory device also includes an input buffer configured to buffer data from the host device. The memory device further includes a write shifter configured to receive a first write command of the write commands and to shift the first command through the write shifter. The write shifter is also configured to cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter. The write shifter is additionally configured to receive a second write command and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a command interface configured to receive write commands from a host device; an input buffer configured to buffer data from the host device; a write shifter configured to: receive a first write command of the write commands and shift the first command through the write shifter; cause the input buffer to be disabled after a first threshold of clock cycles when the first write command has shifted through the write shifter; receive a second write command; and prevent the input buffer from being re-enabled until the second write command has shifted through a second threshold of stages of the write shifter.
2. The memory device of claim 1, wherein the write shifter comprises a plurality of serially connected flip-flops through which the first and second write commands are shifted.
3. The memory device of claim 2, wherein each stage of the write shifter comprises a respective one of the serially connected flip-flops.
4. The memory device of claim 3, wherein the write shifter comprises a turn-on tap point sampled from between two of the serially connected flip-flops.
5. The memory device of claim 4, wherein a number of serially connected flip-flops before the turn-on tap point is equal to a number of stages corresponding to the second threshold of stages.
6. The memory device of claim 4, wherein the write shifter comprises a switch to choose different locations in the plurality of serially connected flip-flops for the turn-on tap point.
7. The memory device of claim 3, wherein a total number of flip-flops in the write shifter is equal to a number of clock cycles for the first threshold.
8. The memory device of claim 1, wherein the write shifter comprises logical OR circuitry configured to perform a logical OR of all stages to determine when the first write command has shifted through the write shifter.
9. The memory device of claim 8, wherein shifting through the write shifter comprises the write command shifting through all stages of the write shifter.
10. The memory device of claim 1, comprising mode selection circuitry configured to select between a fast mode for launching write commands to the write shifter and a slow mode for launching write commands to the write shifter.
11. The memory device of claim 10, wherein the mode selection circuitry is configured to select between the fast mode and the slow mode based on a speed grade for the memory device.
12. The memory device of claim 10, wherein the mode selection circuitry is configured to select between the fast mode and the slow mode based on fused values from fuses in the memory device.
13. The memory device of claim 10, wherein the mode selection circuitry is configured to select between the fast mode and the slow mode based on mode register values set by the host device.
14. The memory device of claim 10, wherein the fast mode corresponds to the write command launching into the write shifter one or more clock cycles sooner than the slow mode would launch the write command into the write shifter.
15. A method for operating a memory device, comprising: disabling an input buffer; receiving, at the memory device, a write command; transmitting the write command through a write shifter of the memory device; after disabling the input buffer, suppressing enablement of the input buffer until the write command has reached a turn-on tap point in the write shifter; and enabling the input buffer after the write command has reached the turn-on tap point in the write shifter.
16. The method of claim 15, comprising selecting a location for the turn-on tap point between two possible locations in the write shifter using a switch coupled to both locations.
17. The method of claim 15, comprising performing an OR of different stages of the write shifter to determine that a previous write command has exited the write shifter to disable the input buffer.
18. The method of claim 15, wherein disabling the input buffer comprises driving an input buffer enable signal to a first logic value and enabling the input buffer comprises driving the input buffer enable signal to a second logic value.
19. The method of claim 18, wherein the first logic value comprises a logic high value and the second logic value comprises a logic low value.
20. A memory device, comprising: a command interface configured to receive write commands from a host device; an input buffer configured to buffer data from the host device; input buffer control circuitry, comprising: a plurality of flip-flops configured to receive a first write command of the write commands and shift the first command through the plurality of flip-flops; logical OR circuitry configured to receive values from each flip-flop of the plurality of flip-flops and to cause the input buffer to be disabled after the first write command has shifted through all of the plurality of flip-flops; and control circuitry configured to prevent the input buffer from being re-enabled after the input buffer is disabled until a subsequently received second write command has shifted through a threshold number of flip-flops of the plurality of flip-flops.
21. The memory device of claim 20, wherein the control circuitry comprises a flip-flop configured to synchronize an OR operation from the logical OR circuitry with a clock of the memory device.
22. The memory device of claim 20, wherein the input buffer control circuitry comprises a switch configured to select between multiple potential turn-on tap point locations, wherein the threshold number of flip-flops corresponds to the selected turn-on tap point location.
23. The memory device of claim 20, wherein the input buffer control circuitry comprises a mode decoder configured to select between a fast mode and a slow mode for the memory device.
24. The memory device of claim 23, wherein the mode decoder is configured to make the selection based at least in part on a speed grade for the memory device or fused values in fuses of the memory device.
25. The memory device of claim 23, wherein the fast mode launches write commands into the plurality of flip-flops after fewer clock than the slow mode launches write commands into the plurality of flip-flops.
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June 29, 2022
February 11, 2025
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