Non-volatile memory with concurrent sub-block programming

1. A non-volatile storage apparatus, comprising: multiple planes of non-volatile memory cells, each plane comprises word lines and blocks of non-volatile memory cells, each block comprises sub-blocks including an upper sub-block and a lower sub-block, the word lines are grouped into predetermined pairs of corresponding word lines such that a predetermined pair of corresponding word lines comprises a word line of a lower sub-block and a word line of an upper sub-block, each predetermined pair of corresponding word lines is assigned a predetermined offset, each of the blocks comprises a plurality of vertical columns that are intersected by the word lines, the vertical columns have diameters that increase from bottom of the vertical columns to top of the vertical columns within the sub-blocks; and one or more control circuits connected to the multiple planes, the one or more control circuits are configured to concurrently program memory cells connected to a first predetermined pair of corresponding word lines including memory cells connected to a first word line in a lower sub-block of a first block of a first plane and memory cells connected to a second word line in an upper sub-block of a second block of a second plane using a common programming voltage signal concurrently applied to the first word line intersecting vertical columns at a first range of one or more column diameters and the second word line intersecting vertical columns at a second range of one or more column diameters, the first range of one or more column diameters is different than and disjoint from the second range of one or more column diameters, the common programming voltage signal comprises a standard programming voltage signal modified by a first predetermined offset assigned to the first predetermined pair of corresponding word lines.

2. The non-volatile storage apparatus of claim 1, wherein: each predetermined pair of corresponding word lines is assigned a predetermined voltage offset; and the first predetermined offset is a first voltage offset assigned to the first predetermined pair of corresponding word lines, which comprise the first word line in the lower sub-block of the first block of the first plane and the second word line in the upper sub-block of the second block of the second plane.

3. The non-volatile storage apparatus of claim 1, wherein: the common programming voltage signal comprises a set of voltage pulses having a pulse width; each predetermined pair of corresponding word lines is assigned a predetermined timing offset; and the first predetermined offset is a first timing offset assigned to the first predetermined pair of corresponding word lines that changes the pulse width.

4. The non-volatile storage apparatus of claim 1, wherein: each predetermined pair of corresponding word lines is assigned a predetermined pre-charge timing offset; and the one or more control circuits are configured to, prior to concurrently programming memory cells, concurrently pre-charge the memory cells for a time period comprising a standard time period adjusted by a first predetermined pre-charge timing offset assigned to the first predetermined pair of corresponding word lines.

5. The non-volatile storage apparatus of claim 1, wherein: each block comprises a stack of dielectric layers alternating with conductive layers and the vertical columns of materials through the stack that form the memory cells, at least a subset of the conducting layers form 2N word lines; the one or more control circuits are configured to program memory cells of upper sub-blocks in a sequence from bottom word line to top word line such that word lines of upper sub-blocks have a sequence number based on when memory cells connected to the respective word line are programmed in the sequence from bottom word line to top word line; the one or more control circuits are configured to program memory cells of lower sub-blocks in a sequence from top word line to bottom word line such that word lines of lower sub-blocks have a sequence number based on when memory cells of the respective word line are programmed in the sequence from top word line to bottom word line; each word line of a lower sub-block has a corresponding word line of an upper sub-block that has a same sequence number such that a pair of corresponding word lines comprises a word line of a lower sub-block and a word line of an upper sub-block both having the same sequence number; the vertical columns are divided into zones based on diameter such that each zone includes a contiguous set of word lines within a single range of diameters of the vertical columns; each block includes a set of offset regions, each offset region includes one or more pairs of corresponding word lines such that each word line of the respective offset region that is in an upper sub-block is in a same zone and each word line of the respective offset region that is in a lower sub-block is in a same zone; and each offset region is associated with a predetermined offset; and the first word line in the lower sub-block of the first block of the first plane has a physical word line number WLn, the second word line in the upper sub-block of the second block of the second plane has a physical word line number WLm, m+n=2N-1.

6. The non-volatile storage apparatus of claim 1, wherein: each block comprises a stack of dielectric layers alternating with conductive layers and the vertical columns of materials through the stack that form the memory cells; the one or more control circuits are configured to program memory cells of upper sub-blocks in a sequence from bottom word line to top word line such that word lines of upper sub-blocks have a sequence number based on when memory cells connected to the respective word line are programmed in the sequence from bottom word line to top word line; the one or more control circuits are configured to program memory cells of lower sub-blocks in a sequence from top word line to bottom word line such that word lines of lower sub-blocks have a sequence number based on when memory cells of the respective word line are programmed in the sequence from top word line to bottom word line; each word line of a lower sub-block has a corresponding word line of an upper sub-block that has a same sequence number such that a pair of corresponding word lines comprises a word line of a lower sub-block and a word line of an upper sub-block both having the same sequence number; the vertical columns are divided into zones based on diameter such that each zone includes a contiguous set of word lines within a single range of diameters of the vertical columns; each block includes a set of offset regions, each offset region includes one or more pairs of corresponding word lines such that each word line of the respective offset region that is in an upper sub-block is in a same zone and each word line of the respective offset region that is in a lower sub-block is in a same zone; each offset region is associated with a voltage magnitude offset; the first predetermined pair of corresponding word lines, which comprise the first word line in the lower sub-block of the first block of the first plane and the second word line in the upper sub-block of the second block of the second plane, are in a first offset region assigned a first voltage magnitude as the first predetermined offset.

7. The non-volatile storage apparatus of claim 6, wherein: each offset region is associated with a program pulse width offset; the first offset region is assigned a first pulse width offset; the common programming voltage signal comprises a plurality of voltage pulses having a pulse width of a standard pulse width modified by the first pulse width offset.

8. The non-volatile storage apparatus of claim 7, wherein: the non-volatile memory cells are arranged in NAND strings; and the one or more control circuits are configured to pre-charge NAND strings connected to the first word line and NAND strings connected to the second word line for a time period equal to a standard pre-charge time period modified by a pre-charge offset assigned to the first offset region.

9. The non-volatile storage apparatus of claim 1, wherein: each block comprises a stack of dielectric layers alternating with conductive layers and the vertical columns of materials through the stack that form the memory cells; the one or more control circuits are configured to program memory cells of upper sub-blocks in a sequence from bottom word line to top word line such that word lines of upper sub-blocks have a sequence number based on when memory cells connected to the respective word line are programmed in the sequence from bottom word line to top word line; the one or more control circuits are configured to program memory cells of lower sub-blocks in a sequence from top word line to bottom word line such that word lines of lower sub-blocks have a sequence number based on when memory cells of the respective word line are programmed in the sequence from top word line to bottom word line; each word line of a lower sub-block has a corresponding word line of an upper sub-block that has a same sequence number such that a pair of corresponding word lines comprises a word line of a lower sub-block and a word line of an upper sub-block both having the same sequence number; the vertical columns are divided into zones based on diameter such that each zone includes a contiguous set of word lines within a single range of diameters of the vertical columns; each block includes a set of offset regions, each offset region includes one or more pairs of corresponding word lines such that each word line of the respective offset region that is in an upper sub-block is in a same zone and each word line of the respective offset region that is in a lower sub-block is in a same zone; each offset region is associated with a predetermined offset of a set of predetermined offsets that includes the first predetermined offset; and the first predetermined pair of corresponding word lines are in a first offset region that is assigned first predetermined offset.

10. The non-volatile storage apparatus of claim 9, wherein: the offset regions are non-overlapping.

11. The non-volatile storage apparatus of claim 9, wherein: the zones are non-overlapping.

12. The non-volatile storage apparatus of claim 9, wherein: each offset regions is assigned a different predetermined offset of the set of predetermined offsets.

13. The non-volatile storage apparatus of claim 9, wherein: each offset regions is capable of being assigned a different predetermined offset of the set of predetermined offsets.

14. The non-volatile storage apparatus of claim 9, wherein: the one or more control circuits are configured to store separate and independent predetermined offsets for each offset region.

15. A method of operating non-volatile storage comprising multiple planes of non-volatile memory cells including a first plane and a second plane, each plane comprising blocks of non-volatile memory cells, each block comprises a stack of dielectric layers alternating with conductive layers and vertical columns of materials through the stack that form the memory cells, each block comprises sub-blocks including an upper sub-block and a lower sub-block, the vertical columns have diameters that increase from bottom of the vertical columns to top of the vertical columns within the sub-blocks, the method comprising: receiving first data; receiving a first address for the first data, the first address corresponds to a first set of memory cells connected a first word line in a lower sub-block of a first block in the first plane, the first word line intersects vertical columns at a first range of one or more column diameters; receiving second data separately from the first data; receiving a second address for the second data, the second address corresponds to a second set of memory cells connected to a second word line in an upper sub-block of a second block in the second plane, the second word line intersects columns at a second range of one or more column diameters, the first range of one or more column diameters is different than and disjoint from the second range of one or more column diameters; and concurrently programming the first data to the first set of memory cells and the second data to the second set of memory cells by concurrently applying a common programming signal to the first word line that intersects vertical columns at the first range of one or more column diameters and the second word line that intersects vertical columns at the second range of one or more column diameters such that the common programming signal comprises a standard programming signal modified by a offset assigned to both the first word line and the second word line based on the first range of one or more column diameters and the second range of one or more column diameters.

16. The method of claim 15, wherein: the offset comprises a change to a voltage magnitude of the standard programming signal.

17. The method of claim 15, wherein: the common programming signal comprises a series of voltage pulses; and the offset comprises a change to a voltage pulse width of the standard programming signal.

18. A non-volatile storage apparatus, comprising: multiple planes of non-volatile memory cells, the non-volatile memory cells are arranged in NAND strings, each plane comprising blocks of non-volatile memory cells, each block comprises a stack of dielectric layers alternating with conductive layers and vertical columns of materials through the stack that form the memory cells, at least a subset of the conducting layers form 2N word lines, each block comprises sub-blocks including an upper sub-block and a lower sub-block, the vertical columns have diameters that increase from bottom of the vertical columns to top of the vertical columns within the sub-blocks; and one or more control circuits connected to the non-volatile memory structure, the one or more control circuits are configured to program memory cells of upper sub-blocks in a sequence from bottom word line to top word line such that word lines of upper sub-blocks have a sequence number based on when memory cells connected to the respective word line are programmed in the sequence from bottom word line to top word line, the one or more control circuits are configured to program memory cells of lower sub-blocks in a sequence from top word line to bottom word line such that word lines of lower sub-blocks have a sequence number based on when memory cells of the respective word line are programmed in the sequence from top word line to bottom word line, each word line of a lower sub-block has a corresponding word line of an upper sub-block that has a same sequence number such that a pair of corresponding word lines comprises a word line of a lower sub-block and a word line of an upper sub-block both having the same sequence number, the vertical columns are divided into zones based on diameter such that each zone includes a contiguous set of word lines within a single range of diameters of the vertical columns, each block includes a set of offset regions, each offset region includes one or more pairs of corresponding word lines such that each word line of the respective offset region that is in an upper sub-block is in a same zone and each word line of the respective offset region that is in a lower sub-block is in a same zone, each offset region is associated with a program voltage offset and a program pulse width offset; the one or more control circuits are configured to concurrently program memory cells connected to a pair of corresponding word lines including WLn in a lower sub-block of first block of a first plane and WLm in an upper sub-block of second block in a second plane, such that m+n=2N-1, using a common programming voltage signal applied to WLn for the first block of the first plane and applied to WLm for the second block of the second plane that comprises a plurality of voltage pulses having a pulse width of a standard pulse width modified by a pulse width offset for an offset region that includes WLn and WLm and magnitudes of standard program signal magnitudes modified by a program voltage offset for the offset region that includes WLn and WLm; the one or more control circuits are configured to pre-charge NAND strings connected to WLn in the lower sub-block of first block of the first plane and NAND strings connected to WLm in the upper sub-block of second block in the second plane for a time period equal to a standard pre-charge time period modified by a pre-charge offset for the offset region that includes WLn and WLm.