Patentable/Patents/US-12230541
US-12230541

Element chip manufacturing method

PublishedFebruary 18, 2025
Assigneenot available in USPTO data we have
Inventorsnot available in USPTO data we have
Technical Abstract

The element chip manufacturing method includes: a preparing process of preparing a substrate 1 including a plurality of element regions EA and a dividing region DA, the substrate 1 having a first principal surface 1X and a second principal surface 1Y; a groove forming process of forming a groove 13 in the dividing region DA from the first principal surface 1X side; and a grinding process of grinding the substrate 1 from the second principal surface 1Y side, to divide the substrate 1 into a plurality of element chips 20. The groove 13 includes a first region 13a constituted by a side surface having a first surface roughness, and a second region 13b constituted by a side surface having a second surface roughness larger than the first surface roughness. In the grinding process, grinding of the substrate 1 is performed until reaching the first region 13a of the groove 13.

Patent Claims
4 claims

Legal claims defining the scope of protection, as filed with the USPTO.

1

1. An element chip manufacturing method comprising: a preparing process of preparing a substrate including a plurality of element regions and a dividing region that defines the element regions, the substrate having a first principal surface and a second principal surface located opposite to the first principal surface, the substrate including a semiconductor layer; a groove forming process of forming a groove in the dividing region from the first principal surface side of the substrate, the groove being formed halfway in a thickness direction of the semiconductor layer; and a grinding process of grinding the substrate from the second principal surface side, to divide the substrate into a plurality of element chips, wherein the groove formed in the groove forming process includes a first region constituted by a side surface having a first surface roughness, and a second region constituted by a side surface having a second surface roughness larger than the first surface roughness in the semiconductor layer, wherein the groove forming process includes: a first plasma processing process of trenching the substrate by continuously etching the substrate, to form the first region having no scallop; and a second plasma processing process of trenching the substrate by repeating an etching step of etching the substrate, a depositing step of depositing a protection film, and a protection film removing step of removing at least a portion of the protection film, to form the second region having scallops and, in the grinding process, grinding of the substrate is performed until reaching the first region of the groove.

2

2. The element chip manufacturing method according to claim 1, wherein the groove forming process is started from the first plasma processing process.

3

3. The element chip manufacturing method according to claim 1, wherein, in the groove forming process, the first plasma processing process and the subsequent second plasma processing process are performed last, and, in the grinding process, grinding of the substrate is performed until reaching the first region of the groove, the first region having been formed in the first plasma processing process performed last.

4

4. The element chip manufacturing method according to claim 1, wherein, in the groove forming process, the first plasma processing process is performed last, and, in the grinding process, grinding of the substrate is performed until reaching the first region of the groove, the first region having been formed in the first plasma processing process performed last.

Classification Codes (CPC)

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Patent Metadata

Filing Date

November 30, 2021

Publication Date

February 18, 2025

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