Time-sensitive network switch

1. A time-sensitive network switch, comprising a plurality of multi-core CPUs, is configured to: in response to receiving data through a physical transmission medium of the time-sensitive network switch, determine a target multi-core CPU in the plurality of multi-core CPUs; wherein, the target multi-core CPU is configured to: determine, in response to receiving the data, time-sensitive data and non-time-sensitive data from the data; determine a first buffer for storing the time-sensitive data and a second buffer for storing the non-time-sensitive data, in a cache resource pool of the time-sensitive network switch; and identify a priority of the time-sensitive data to allocate the time-sensitive data into a queue at a first port of the time-sensitive network switch to be waiting for transmission; wherein, the time-sensitive network switch further comprises a DMA controller, configured to output the non-time-sensitive data from a second port of the time-sensitive network switch by the DMA controller; wherein identifying the priority of the time-sensitive data to allocate the time-sensitive data into the queue at the first port of the time-sensitive network switch to be waiting for transmission comprises: according to the priority of the time-sensitive data, establishing a function library and a driver set to solve a port queue scheduling scheme for the time-sensitive data; and according to the port queue scheduling scheme, allocating the time-sensitive data into the queue at the first port of the time-sensitive network switch to be waiting for transmission.

2. The time-sensitive network switch according to claim 1, wherein, in response to receiving data through the physical medium of the time-sensitive network switch, determining the target multi-core CPU in the plurality of multi-core CPUs comprises: according to Quality of Service (QOS) requirements of the data and a configuration file defaulted by a user, determining the target multi-core CPU in the plurality of multi-core CPUs.

3. The time-sensitive network switch according to claim 1, wherein after identifying the priority of the time-sensitive data, the target multi-core CPU is further configured to: determine an idle core in the target multi-core CPU; and enable the idle core to process time-sensitive data with high priority to realize accelerated processing for the time-sensitive data with high priority.

4. The time-sensitive network switch according to claim 1, wherein, after receiving the data, and before determining the time-sensitive data and the non-time-sensitive data from the data, the target multi-core CPU is further configured to: verify for the received data; wherein, determining the time-sensitive data and non-time-sensitive data from the data comprises: determining the time-sensitive data and non-time-sensitive data from the data in response to a successful verification.

5. The time-sensitive network switch according to claim 1, wherein the DMA controller is configured to perform port-to-port pass-through transmission for the non-time-sensitive data.

6. The time-sensitive network switch according to claim 1, wherein the target multi-core CPU is further configured to: monitor abnormal flows through ports and prevent abnormal data attacks at the ports.

7. The time-sensitive network switch according to claim 1, wherein each multi-core CPU is configured with L1 cache, L2 cache and SDRAM, wherein the L1 cache comprises an instruction cache area and a data cache area; the L2 cache is configured to cache data to be processed; in response to determining that the first buffer for storing the time-sensitive data and the second buffer for storing the non-time-sensitive data cannot be determined in the cache resource pool, the target multi-core CPU is further configured to: establish a third buffer for storing the time-sensitive data in the SDRAM; establish a fourth buffer for storing the non-time-sensitive data in the SDRAM.

8. A time-sensitive network switch, comprising: a plurality of multi-core CPUs; a plurality of data traffic planes, wherein each data traffic plane comprises a DMA controller, a cache resource pool coupled with the DMA controller, and a plurality of physical transmission media coupled with the cache resource pool; a data management plane, wherein the data management plane is configured to manage the plurality of data traffic planes; an internal interconnect bus, wherein the data management plane and the plurality of data traffic planes are coupled with the plurality of multi-core CPUs through the internal interconnect bus; wherein, in response to receiving data through a physical transmission medium, the time-sensitive network switch is configured to: determine, by the internal interconnect bus, a target multi-core CPU for processing the data in the plurality of multi-core CPUs; determine, by the target multi-core CPU, time-sensitive data and non-time-sensitive data from the data based on the data management plane; determine, by the target multi-core CPU, a first buffer for storing the time-sensitive data and a second buffer for storing the non-time-sensitive data, in the cache resource pool based on the data management plane; identify, by the target multi-core CPU, a priority of the time-sensitive data based on the data management plane, to allocate, through the data traffic plane corresponding to the physical transmission medium, the time-sensitive data into a queue at a first port of the time-sensitive network switch to be waiting for transmission; and output, by the DMA controller in the data traffic plane corresponding to the physical transmission medium, the non-time sensitive data from a second port of the time sensitive network switch; wherein identifying the priority of the time-sensitive data to allocate the time-sensitive data into the queue at the first port of the time-sensitive network switch to be waiting for transmission comprises: according to the priority of the time-sensitive data, establishing a function library and a driver set to solve a port queue scheduling scheme for the time-sensitive data; and according to the port queue scheduling scheme, allocating the time-sensitive data into the queue at the first port of the time-sensitive network switch to be waiting for transmission.