Power electronics device assemblies, circuit board assemblies, and power electronics assemblies are disclosed. In one embodiment, a power electronics device assembly includes an S-cell including a first metal layer comprising a first surface having a recess, a first graphite layer bonded to the first metal layer, a second metal layer bonded to the first graphite layer, a solder layer disposed on the second metal layer, and an electrically insulating layer bonded to the solder layer. The power electronics device assembly may further include a power electronics device disposed within the recess of the first surface of the first metal layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A power electronics device assembly comprising: an S-cell comprising: a first metal layer comprising a first surface having a recess; a graphite layer bonded to the first metal layer; a second metal layer bonded to the graphite layer; a solder layer disposed on the second metal layer; and an electrically insulating layer bonded to the solder layer; and a power electronics device disposed within the recess of the first surface of the first metal layer.
2. The power electronics device assembly of claim 1, wherein the electrically insulating layer is made from silicon nitride.
3. The power electronics device assembly of claim 1, wherein the S-cell has a length that is greater than a width.
4. The power electronics device assembly of claim 1, further comprising: a first brazing layer between the first metal layer and the graphite layer; and a second brazing layer between the second metal layer and the graphite layer.
5. A circuit board assembly comprising: a substrate that is electrically insulating; a power electronics device assembly fully embedded in the substrate, the power electronics device assembly comprising: an S-cell comprising: a first metal layer comprising a first surface having a recess; a graphite layer bonded to the first metal layer; a second metal layer bonded to the graphite layer; a solder layer disposed on the second metal layer; and an electrically insulating layer bonded to the solder layer; and a power electronics device disposed within the recess of the first surface of the first metal layer.
6. The circuit board assembly of claim 5, further comprising a plurality of electrically conductive layers embedded within the substrate.
7. The circuit board assembly of claim 5, further comprising a plurality of vias embedded in the substrate and thermally coupled to the power electronics device.
8. The circuit board assembly of claim 5, wherein the electrically insulating layer is made from silicon nitride.
9. The circuit board assembly of claim 5, wherein the S-cell has a length that is greater than a width.
10. The circuit board assembly of claim 5, wherein the S-cell further comprises: a first brazing layer between the first metal layer and the graphite layer; and a second brazing layer between the second metal layer and the graphite layer.
11. A power electronics assembly comprising: a cold plate; and a circuit board assembly affixed to a first surface of the cold plate, the circuit board assembly comprising: a substrate that is electrically insulating; a power electronics device assembly fully embedded in the substrate, the power electronics device assembly comprising: an S-cell comprising: a first metal layer comprising a first surface having a recess; a graphite layer bonded to the first metal layer; a second metal layer bonded to the graphite layer; a solder layer disposed on the second metal layer; and an electrically insulating layer bonded to the solder layer; and a power electronics device disposed within the recess of the first surface of the first metal layer.
12. The power electronics assembly of claim 11, wherein the circuit board assembly is affixed to the first surface of the cold plate by a bond layer.
13. The power electronics assembly of claim 11, wherein the circuit board assembly is affixed to the first surface of the cold plate by fasteners and a thermal grease layer.
14. The power electronics assembly of claim 11, wherein the S-cell includes an asymmetrical profile.
15. The power electronics assembly of claim 11, wherein; the cold plate comprises a fluid chamber, a fluid inlet, and a fluid outlet; and the fluid inlet and the fluid outlet are thermally coupled to the fluid chamber.
16. The power electronics assembly of claim 11, wherein the circuit board assembly further comprises a plurality of electrically conductive layers embedded within the substrate.
17. The power electronics assembly of claim 11, wherein the circuit board assembly further comprises a plurality of vias embedded in the substrate and thermally coupled to the power electronics device.
18. The power electronics assembly of claim 11, wherein the electrically insulating layer is made from silicon nitride.
19. The power electronics assembly of claim 11, wherein the S-cell has a length that is greater than a width.
20. The power electronics assembly of claim 11, wherein the S-cell further comprises: a first brazing layer between the first metal layer and the graphite layer; and a second brazing layer between the second metal layer and the graphite layer.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
January 17, 2023
February 25, 2025
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