An in-memory compute (IMC) device includes an array of memory cells and control logic coupled to the array of memory cells. The array of memory cells is arranged as a plurality of rows of cells intersecting a plurality of columns of cells. The array of memory cells includes a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells. The array also includes a second subset of memory cells forming a plurality of bias engines. The control logic, in operation, generates control signals to control the array of memory cells to perform a plurality of IMC operations using the computational engines, store results of the plurality of IMC operations in memory cells of the array, and computationally combine results of the plurality of IMC operations with respective bias values using the bias engines.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A non-transitory computer-readable medium having contents which configure an in-memory compute (IMC) device to perform a method, the method comprising: storing a plurality of values in respective memory bitcells of the IMC device, wherein the IMC device has a first plurality of bitcells arranged as a plurality of rows of bitcells intersecting a plurality of columns of bitcells, each bitcell of the first plurality of bitcells identifiable by a corresponding row and column; performing a plurality of IMC operations, each of the IMC operations using one or more of the stored plurality of values as an operand; storing results of the plurality of IMC operations in a second plurality of bitcells, the second plurality of bitcells being formed from bitcells of the first plurality of bitcells; and computationally combining results of the plurality of IMC operations with respective bias values.
2. The non-transitory computer-readable medium of claim 1, wherein a portion of the IMC device is a static random access memory (SRAM) memory device.
3. The non-transitory computer-readable medium of claim 1, wherein the plurality of IMC operations include at least one gating function and at least one mathematical function.
4. The non-transitory computer-readable medium of claim 1, wherein computationally combining results of the plurality of IMC operations with respective bias values includes: combining a row of results information with a row of bias values.
5. The non-transitory computer-readable medium of claim 1, wherein computationally combining results of the plurality of IMC operations with respective bias values includes: producing a set of computationally combined values; and storing the set of computationally combined values in memory bitcells of the first plurality of bitcells without passing the set of computationally combined values out of the IMC device.
6. The non-transitory computer-readable medium of claim 1, wherein computationally combining results of the plurality of IMC operations with respective bias values includes: producing a set of computationally combined values; storing the set of computationally combined values in memory bitcells of the first plurality of bitcells; and passing at least some of the set of computationally combined values out of the IMC device.
7. The non-transitory computer-readable medium of claim 1, wherein the storing the plurality of values in respective memory bitcells of the IMC device comprises: storing a plurality of neural network kernel values; storing a plurality of neural network feature values; or storing a plurality of neural network kernel values and a plurality of neural network feature values.
8. The non-transitory computer-readable medium of claim 7, wherein the performing an operation of the plurality of IMC operations comprises: using a stored neural network kernel value as an operand; using a stored neural network feature value as an operand; or using a stored neural network kernel value and a stored neural network feature value as operands.
9. The non-transitory computer-readable medium of claim 1, wherein the contents comprise a set of IMC instructions.
10. A system, comprising: data processing means; and in-memory computing (IMC) means coupled to the data processing means, wherein the IMC means, in operation: stores a plurality of values in respective memory bitcells of a first plurality of bitcells arranged as a plurality of rows of bitcells intersecting a plurality of columns of bitcells, each bitcell of the first plurality of bitcells identifiable by a corresponding row and column; performs a plurality of IMC operations, each of the IMC operations using one or more of the stored plurality of values as an operand; stores results of the plurality of IMC operations in a second plurality of bitcells, the second plurality of bitcells being formed from bitcells of the first plurality of bitcells; and computationally combines results of the plurality of IMC operations with respective bias values.
11. The system of claim 10, wherein the first plurality of bitcells comprises an array of memory bitcells.
12. The system of claim 11, wherein the array of memory bitcells is a static random access memory (SRAM) memory array.
13. The system of claim 10, wherein the plurality of IMC operations includes at least one gating operation.
14. The system of claim 10, wherein the plurality of IMC operations includes at least one mathematical operation.
15. The system of claim 10, comprising sensing means coupled to the data processing means.
16. The system of claim 10, comprising storage means, which, in operation, stores instructions executable by the data processing means.
17. An in-memory compute (IMC) device, comprising: an array of memory cells, arranged as a plurality of rows of cells intersecting a plurality of columns of cells, the array of memory cells including: a first subset of memory cells forming a plurality of computational engines at intersections of rows and columns of the first subset of the array of memory cells; and a second subset of memory cells forming a plurality of bias engines; and control logic coupled to the array of memory cells, wherein, in operation, the control logic generates control signals to control the array of memory cells to: perform a plurality of IMC operations using computational engines of the plurality of computational engines; store results of the plurality of IMC operations in memory cells of the array; and computationally combine results of the plurality of IMC operations with respective bias values using the plurality of bias engines.
18. The IMC device of claim 17, wherein the plurality of IMC operations include at least one gating function and at least one mathematical function.
19. The IMC device of claim 17, wherein computationally combining results of the plurality of IMC operations with respective bias values includes: combining a row of results information with a row of bias values.
20. The IMC device of claim 17, wherein the control logic, in operation, generates control signals to control the array of memory cells to store results of the computationally combining of the results of the plurality of IMC operations with respective bias values in memory cells of the array of memory cells.
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February 10, 2023
March 4, 2025
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