Superconducting distributed bidirectional current driver system

1. A superconducting distributed bidirectional current driver circuit for selectively steering current in one of first and second directions through at least one bidirectional current load, the superconducting distributed bidirectional current driver circuit comprising: a plurality of bidirectional current drivers, the at least one bidirectional current load being operatively coupled between two adjacent bidirectional current drivers of the plurality of bidirectional current drivers, each of the bidirectional current drivers comprising: a first superconducting latch circuit configured to convey current through the bidirectional current load as a function of at least a first activation signal applied thereto; and a second superconducting latch circuit configured to convey current through a bidirectional current load associated with an adjacent one of the plurality of bidirectional current drivers as a function of at least a second activation signal applied thereto, wherein the first superconducting latch circuit in a first one of the bidirectional current drivers operatively coupled to the bidirectional current load and the second superconducting latch circuit in a second one of the bidirectional current drivers operatively coupled to the bidirectional current load are selectively activated by the first and second activation signals, respectively, to establish a first current path of a first input current, supplied to the first one of the bidirectional current drivers, through the bidirectional current load in a first direction, and wherein the second superconducting latch circuit in the second one of the bidirectional current drivers operatively coupled to the bidirectional current load and the first superconducting latch circuit in the first one of the bidirectional current drivers operatively coupled to the bidirectional current load are selectively activated by the second and first activation signals, respectively, to establish a second current path of a second input current, supplied to the second one of the bidirectional current drivers, through the bidirectional current load in a second direction opposite the first direction.

2. The circuit according to claim 1, wherein each of the first and second superconducting latch circuits in at least a subset of the plurality of bidirectional current drivers is configured as a quantum flux device activated in response to the first and second activation signals, respectively, provided from a corresponding activation controller to set the respective first superconducting latch circuit or second superconducting latch circuit to a voltage state in response to triggering of at least one Josephson junction.

3. The circuit according to claim 1, wherein two adjacent superconducting bidirectional current drivers of the plurality of superconducting bidirectional current drivers are connected to form respective legs in an H-bridge circuit operatively coupled to the bidirectional current load, wherein the first superconducting latch circuit in a first adjacent superconducting bidirectional current driver comprises a first superconducting latch operatively coupled between a corresponding first current source and a first end of the bidirectional current load, and a second superconducting latch coupled between the first end of the bidirectional current load and a low-voltage rail, and wherein the second superconducting latch circuit of a second adjacent bidirectional current driver comprises a third superconducting latch coupled between a corresponding second current source and a second end of the bidirectional current load, and a fourth superconducting latch coupled between the second end of the bidirectional current load and the low-voltage rail.

4. The circuit according to claim 3, wherein at least one of the plurality of superconducting bidirectional current drivers further comprises a shunt current path interconnecting a corresponding current source and the low-voltage rail, wherein the shunt current path is configured to provide a current path for a corresponding one of the first and second input currents in response to concurrent activation of the superconducting latches in a given one of the adjacent superconducting bidirectional current drivers.

5. The circuit according to claim 1, further comprising a reset latch interconnecting the bidirectional current load and a given one of the adjacent superconducting bidirectional current drivers, the reset latch being activated to return the given superconducting bidirectional current driver from a current state in which a corresponding input current is provided through the bidirectional current load to an idle state in which no current is provided through the bidirectional current load.

6. The circuit according to claim 1, wherein two adjacent superconducting bidirectional current drivers of the plurality of superconducting bidirectional current drivers are connected to form respective legs in an A-bridge circuit operatively coupled to the bidirectional current load, wherein the first superconducting latch circuit in a first adjacent superconducting bidirectional current driver comprises a first inductor operatively coupled between a corresponding first current source and a first end of the bidirectional current load, and a first superconducting latch coupled between the first end of the bidirectional current load and a low-voltage rail, and wherein the second superconducting latch circuit of a second adjacent bidirectional current driver comprises a second inductor coupled between a corresponding second current source and a second end of the bidirectional current load, and a second superconducting latch coupled between the second end of the bidirectional current load and the low-voltage rail.

7. The circuit according to claim 1, wherein each of the first and second current sources is configured as a flux shuttle loop current source configured to generate the first or second input current, respectively, in a corresponding storage inductor, the storage inductor being configured to provide the first or second input current to a corresponding one of the bidirectional current drivers.

8. A memory write driver comprising a bidirectional current driver circuit according to claim 1, wherein the bidirectional current load is configured as a bidirectional inductive current load that is inductively coupled to at least one of a row or a column of a memory array in which the memory write driver is operatively connected, wherein the bidirectional inductive current load is configured to provide a write current on a write line in a first direction to write a first memory state based on the input current being provided through the bidirectional inductive current load in the first direction, and to provide the write current on the write line in a second direction opposite the first direction to write a second memory state based on the input current being provided through the bidirectional inductive current load in the second direction.

9. A superconducting distributed bidirectional memory write current driver circuit for writing memory state to one or more selected memory cells in a memory array, the superconducting distributed bidirectional memory write current driver circuit comprising: a plurality of bidirectional write current drivers; at least first and second current sources configured to generate first and second input currents, respectively; and a first write line associated with at least one of a row or a column of the memory array and operatively coupled between two adjacent bidirectional write current drivers of the plurality of bidirectional write current drivers, the write line being configured to write a first memory state of at least one memory cell associated with the first write line as a function of the first input current being provided through the first write line in a first direction, and to write a second memory state of the at least one memory cell associated with the first write line as a function of the second input current being provided through the first write line in a second direction opposite the first direction, wherein each of the plurality of bidirectional write current drivers comprises: a first superconducting latch circuit configured to convey current through the first write line as a function of at least a first activation signal applied thereto; and a second superconducting latch circuit configured to convey current through a second write line associated with an adjacent one of the plurality of bidirectional write current drivers as a function of at least a second activation signal applied thereto; wherein the first superconducting latch circuit in a first one of the bidirectional current drivers operatively coupled to the first write line and the second superconducting latch circuit in a second one of the bidirectional current drivers operatively coupled to the first write line are selectively activated by the first and second activation signals, respectively, to establish a first current path of the first input current supplied to the first one of the bidirectional current drivers, through the first write line in the first direction, and wherein the second superconducting latch circuit in the second one of the bidirectional current drivers operatively coupled to the first write line and the first superconducting latch circuit in the first one of the bidirectional current drivers operatively coupled to the first write line are selectively activated by the second and first activation signals, respectively, to establish a second current path of the second input current supplied to the second one of the bidirectional current drivers, through the first write line in the second direction.

10. The circuit according to claim 9, wherein two adjacent bidirectional write current drivers of the plurality of bidirectional write current drivers are connected to form respective legs in an H-bridge circuit operatively coupled to the first write line, wherein the first superconducting latch circuit in a first adjacent bidirectional write current driver comprises a first superconducting latch operatively coupled between the first current source and a first end of the first write line, and a second superconducting latch coupled between the first end of the first write line and a low-voltage rail, and wherein the second superconducting latch circuit of a second adjacent bidirectional write current driver comprises a third superconducting latch coupled between the second current source and a second end of the first write line, and a fourth superconducting latch coupled between the second end of the first write line and the low-voltage rail.

11. The circuit according to claim 10, wherein at least one of the plurality of bidirectional write current drivers further comprises a shunt current path interconnecting a corresponding one of the first or second current sources and the low-voltage rail, wherein the shunt current path is configured to provide a current path for a corresponding one of the first and second input currents in response to concurrent activation of the superconducting latches in a given one of the adjacent bidirectional write current drivers.

12. The circuit according to claim 9, further comprising a reset latch interconnecting the first write line and a given one of the adjacent bidirectional write current drivers, the reset latch being activated to return the given bidirectional write current driver from a current state in which a corresponding input current is provided through the first write line to an idle state in which no current is provided through the first write line.

13. The circuit according to claim 9, wherein two adjacent bidirectional write current drivers of the plurality of bidirectional write current drivers are connected to form respective legs in an A-bridge circuit operatively coupled to the first write line, wherein the first superconducting latch circuit in a first adjacent bidirectional write current driver comprises a first inductor operatively coupled between the first current source and a first end of the first write line, and a first superconducting latch coupled between the first end of the first write line and a low-voltage rail, and wherein the second superconducting latch circuit of a second adjacent bidirectional write current driver comprises a second inductor coupled between the second current source and a second end of the first write line, and a second superconducting latch coupled between the second end of the first write line and the low-voltage rail.

14. A superconducting analog circuit, comprising: a plurality of superconducting distributed bidirectional current driver circuits, each of the plurality of superconducting distributed bidirectional current driver circuits is configured to generate a current in one of a first direction and a second direction, the second direction being opposite the first direction; and a time-division demultiplexing circuit operatively coupled to the plurality of superconducting distributed bidirectional current driver circuits, wherein the time-division demultiplexing circuit is configured such that a direction of the current generated by each of the plurality of superconducting distributed bidirectional current driver circuits is controlled as a function of a temporal sequence of data on a given data line in the superconducting analog circuit.