Sub-sampling phase-locked loop circuit capable of avoiding harmonic locking

1. A sub-sampling phase-locked loop circuit capable of avoiding harmonic locking, comprising a harmonic suppression sampling charge pump module, a filter module and a voltage-controlled oscillator module, wherein an input end of the harmonic suppression sampling charge pump module is used as an input end of a sub-sampling phase-locked loop circuit, a reference clock signal FREF and differential signals VCOP and VCON are respectively accessed to an input end of the harmonic suppression sampling charge pump module, an output end of the harmonic suppression sampling charge pump module outputs an output signal Iout and the signal is accessed to an input end of the filter module, an output end of the filter module is connected with an input end of the voltage-controlled oscillator module, an output end of the voltage-controlled oscillator module outputs differential signals as the differential signals VCOP and VCON accessed to the input end of the harmonic suppression sampling charge pump module, output signals VCOP and VCON of the voltage-controlled oscillator module are used as final outputs of the sub-sampling phase-locked loop circuit, and the differential signals VCOP and VCON are synchronous with the reference clock signal FREF in phase at the same time; the harmonic suppression sampling charge pump module comprises a sub-sampling phase comparison unit, a switched capacitor frequency comparison unit and a charge pump unit; the reference clock signal FREF and the differential signals VCOP and VCON are respectively accessed to the sub-sampling phase comparison unit, and an output end of the sub-sampling phase comparison unit outputs signals VSAMP and VSAMN respectively; the reference clock signal FREF and the differential signal VCOP are respectively accessed to the switched capacitor frequency comparison unit, and an output end of the switched capacitor frequency comparison unit outputs signals FCMN and FCMP respectively; and the signals VSAMP and VSAMN and the signals FCMN and FCMP are respectively accessed to the charge pump unit, and an output end of the charge pump unit outputs the signal Iout; the charge pump unit comprises a transistor M0, a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a transistor M7, a transistor M8, a transistor M9, a transistor M10, a transistor M11, a transistor M12, a transistor M13, a transistor M14, a transistor M15, a transistor M16, a switch S7, a switch S8, a switch S9 and a switch S10; a gate of the transistor M0 is connected with a bias voltage VBP, a drain of the transistor M0 is connected with a source of the transistor M1, a source of the transistor M2, a source of the transistor M3 and a source of the transistor M4 respectively, a gate of the transistor M1 is accessed with the signal VSAMP, a gate of the transistor M2 is accessed with the signal FCMP, drains of the transistor M1 and the transistor M2 are connected and then connected with a drain of the transistor M5 and a gate of the transistor M6 respectively, a gate of the transistor M5 is connected with a bias voltage VBN, and a source of the transistor M5 is connected with a drain of the transistor M6; a gate of the transistor M3 is accessed with the signal FCMN, a gate of the transistor M4 is accessed with the signal VSAMN, drains of the transistor M3 and the transistor M4 are connected and then connected with a drain of the transistor M7 and a gate of the transistor M8 respectively, a gate of the transistor M7 is connected with the bias voltage VBN, and a source of the transistor M7 is connected with a drain of the transistor M8; a gate of the transistor M10 is connected with the gate of the transistor M8, a drain of the transistor M10 is connected with a source of the transistor M9, a gate of the transistor M9 is connected with the bias voltage VBN, a drain of the transistor M9 is connected with a gate of the transistor M11, a drain of transistor M12 and a gate of transistor M13 respectively, and a source of the transistor M12 is connected with a drain of the transistor M11; and a drain of the transistor M13 is connected with a source of the transistor M14, a drain of the transistor M14 is connected with one end of the switch S7 and one end of the switch S9 respectively, a gate of the transistor M14 is connected with a gate of the transistor M12, the other end of the switch S7 is connected with one end of the switch S8, the other end of the switch S9 is connected with one end of the switch S10, a drain of the transistor M15 is connected with the other end of the switch S8 and the other end of the switch S10 respectively, a gate of the transistor M15 is connected with the bias voltage VBN, a source of the transistor M15 is connected with a drain of the transistor M16, a gate of the transistor M16 is connected with the gate of the transistor M6, and a source of the transistor M0, a source of the transistor M11 and a source of the transistor M13 are connected with the power supply VDD; a source of the transistor M6, a source of the transistor M8, a source of the transistor M10 and a source of the transistor M16 are grounded; the switch S7 and the switch S10 are controlled to be turned on and off by a signal PUL, the switch S9 and the switch S8 are controlled to be turned on and off by a signal PULB, and the signals PUL and PULB are generated by the reference clock signal FREF through a pulse generator module; and one end of the switch S10 is used as an output end of the charge pump unit to output the signal Iout.

2. The sub-sampling phase-locked loop circuit capable of avoiding harmonic locking according to claim 1, wherein the sub-sampling phase comparison unit comprises a switch S1, a switch S2, a capacitor C1 and a capacitor C2; and one end of the switch S1 is accessed with the differential signal VCOP output by the voltage controlled oscillator module, one end of the switch S2 is accessed with the differential signal VCON output by the voltage-controlled oscillator module, the other end of the switch S1 is used as a first output end of the sub-sampling phase comparison unit to output the signal VSAMP, the other end of the switch S2 is used as a second output end of the sub-sampling phase comparison unit to output the signal VSAMN, the switches S1 and S2 are both controlled to be turned on and off based on the reference clock signal FREF, one end of the capacitor C1 is connected with the other end of the switch S1, one end of the capacitor C2 is connected with the other end of the switch S2, and the other ends of the capacitors C1 and C2 are grounded.

3. The sub-sampling phase-locked loop circuit capable of avoiding harmonic locking according to claim 2, wherein the switched capacitor frequency comparison unit comprises a transistor M17, a transistor M18, a switch S3, a switch S4, a switch S5, a switch S6, a capacitor C3, a capacitor C4, a non-overlapping clock generation circuit N1 and a non-overlapping clock generation circuit N2; and sources of the transistor M17 and the transistor M18 are both connected with a power supply VDD, gates of the transistor M17 and the transistor M18 are both connected with the bias voltage VBP, a drain of the transistor M17 is connected with one end of the switch S3, a drain of the transistor M18 is connected with one end of the switch S5, one end of the switch S4 is connected with one end of the capacitor C3, the other end of the switch S4 is connected with the other end of the switch S3, one end of the switch S6 is connected with one end of the capacitor C4, the other end of the switch S6 is connected with the other end of the switch S5, the other ends of the capacitor C3 and the capacitor C4 are both grounded, the switches S3 and S4 are controlled to be turned on and off by the non-overlapping clock generation circuit N2, the switches S5 and S6 are controlled to be turned on and off by the non-overlapping clock generation circuit N1, an input of the non-overlapping clock generation circuit N2 is the reference clock signal FREF, an input of the non-overlapping clock generation circuit N1 is the differential signal VCOP, and the drain of the transistor M17 is used as a first output end of the switched capacitor frequency comparison unit to output the signal FCMN and the drain of the transistor M18 is used as a second output end of the switched capacitor frequency comparison unit to output the signal FCMP.