An example memory cell includes a superconducting loop configured to receive a write current and form a persistent current that stores a data bit in the superconducting loop. The example memory cell further includes a superconducting wire coupled to the superconducting loop and configured to selectively read-out the data bit in the superconducting loop in response to a control signal. An example method of reading data from the memory cell includes receiving, at the superconducting loop, a write current to store a data bit in a superconducting loop, and forming a persistent current that circulates in the superconducting loop as a stored data bit. The example method further includes, in accordance with a control signal, transferring, via a superconducting wire of the memory cell that is coupled to the superconducting loop, at least a portion of the persistent current to an output of the memory cell.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A memory device, comprising: a superconducting loop configured to receive a write current and form a persistent current that stores a data bit in the superconducting loop; and a superconducting wire separate and distinct from the superconducting loop, the superconducting wire coupled to the superconducting loop and configured to selectively read-out the data bit in the superconducting loop in response to a read signal.
2. The memory device of claim 1, further comprising a second superconducting wire configured to transmit the write current to the superconducting loop.
3. The memory device of claim 2, wherein the second superconducting wire is configured to transition from a superconductive state to a non-superconductive state in accordance with transmitting the write current.
4. The memory device of claim 1, wherein the superconducting loop is formed from a superconducting material.
5. The memory device of claim 1, wherein the superconducting loop is capacitively coupled to the superconducting wire.
6. The memory device of claim 1, further comprising an array of memory cells, wherein the array of memory cells includes a first memory cell, the first memory cell comprising the superconducting loop.
7. The memory device of claim 6, further comprising circuitry to address a respective memory cell in the array of memory cells so as to direct a respective write current to the respective memory cell.
8. The memory device of claim 1, further comprising a control component coupled to the superconducting wire, the control component configured to maintain at least a portion of the superconducting wire in a non-superconductive state until the read signal is received.
9. The memory device of claim 8, wherein the control component comprises a heating element configured to provide heat to the at least a portion of the superconducting wire.
10. The memory device of claim 8, wherein selectively reading out the data bit comprises transitioning the superconducting wire from the non-superconductive state to a superconductive state so as to transfer at least a portion of the persistent current to the superconducting wire.
11. A method of reading data from a memory device, the method comprising: receiving, at a superconducting loop of the memory device, a write current to store a data bit in the superconducting loop; forming, at the superconducting loop, a persistent current that circulates in the superconducting loop as a stored data bit; and in accordance with a control signal, transferring, via a superconducting wire of the memory device that is coupled to the superconducting loop, at least a portion of the persistent current to an output of the memory device, wherein the superconducting wire is separate and distinct from the superconducting loop.
12. The method of claim 11, wherein the write current is received via a second superconducting wire that is capacitively coupled to the superconducting loop.
13. The method of claim 11, wherein the superconducting wire is capacitively coupled to the superconducting loop.
14. The method of claim 11, further comprising, prior to the transferring, maintaining at least a portion of the superconducting wire in a non-superconducting state.
15. The method of claim 11, wherein transferring the at least a portion of the persistent current comprises transitioning at least a portion of the superconducting wire from a non-superconducting state to a superconducting state.
16. The method of claim 15, wherein transitioning the at least a portion of the superconducting wire from the non-superconducting state to the superconducting state comprises deactivating a heating element that is thermally coupled to the superconducting wire.
17. The method of claim 11, wherein forming the persistent current comprises transitioning a write wire to a non-superconducting state so as to prevent the persistent current from transferring back to the write wire.
18. The method of claim 17, wherein transitioning the write wire to the non-superconducting state comprises increasing a current density of the write wire such that the current density exceeds a threshold current density.
19. The method of claim 11, wherein the memory device comprises an array of memory cells, and wherein the superconducting loop is a component of a first memory cell of the array of memory cells.
20. The method of claim 19, further comprising selectively supplying write currents to the array of memory cells to store a set of data bits in the array of memory cells.
Cooperative Patent Classification codes for this invention. Click any code to explore related patents in that topic.
February 26, 2024
April 1, 2025
Browse 5M+ US patents with plain-English claim translations and AI-generated analysis.