Interposer and semiconductor package including same

1. A semiconductor package comprising: a package substrate; an interposer mounted on the package substrate; and a semiconductor chip mounted on the interposer, wherein the interposer comprises a base layer including a first surface and a second surface opposite the first surface, a redistribution structure on the first surface of the base layer, configured to mount the semiconductor chip and including a conductive redistribution pattern, a first lower protection layer on the second surface of the base layer, a lower conductive pad on the first lower protection layer, a through electrode passing through the base layer and the first lower protection layer to electrically connect the conductive redistribution pattern to the lower conductive pad, a second lower protection layer on the first lower protection layer and contacting at least a portion of the lower conductive pad, and an indentation formed in an outer edge region of the interposer to provide a continuous sidewall extending entirely through the second lower protection layer and entirely through the first lower protection layer to expose a linear portion of the second surface of the base layer, wherein the continuous sidewall includes a second curvilinear sidewall extending entirely through the second lower protection layer, and a first curvilinear sidewall extending entirely through the first lower protection layer, wherein an upper limit of the first curvilinear sidewall is at a vertical level the same as or lower than a vertical level of the second surface of the base layer, the upper limit being measured from (i) an interface between the first lower protection layer and the second lower protection layer toward (ii) an interface between the first lower protection layer and base layer, and wherein the linear portion of the second surface of the base layer extends from the first curvilinear sidewall to an outer wall of the interposer.

2. The semiconductor package of claim 1, wherein the continuous sidewall is smooth without discontinuous transitions.

3. The semiconductor package of claim 1, wherein the first curvilinear sidewall includes a curved profile when viewed in cross-section of the interposer.

4. The semiconductor package of claim 3, wherein the second curvilinear sidewall includes a curved profile when viewed in cross-section of the interposer.

5. The semiconductor package of claim 1, wherein a curvature of the first curvilinear sidewall is different from a curvature of the second curvilinear sidewall.

6. The semiconductor package of claim 1, wherein the base layer includes a silicon.

7. The semiconductor package of claim 1, wherein the first lower protection layer includes a different material than the second lower protection layer.

8. The semiconductor package of claim 1, wherein the first lower protection layer includes an inorganic material, and the second lower protection layer includes an organic material.

9. The semiconductor package of claim 1, further comprising: a lower connection pillar contacting the lower conductive pad through an opening in the second lower protection layer; and a connector contacting the lower connection pillar.

10. The semiconductor package of claim 9, wherein the interposer is mounted on the package substrate by the connector.

11. The semiconductor package of claim 10, further comprising: an underfill material layer between the package substrate and the second lower protection layer, wherein the underfill material layer surrounds the connector and covers at least a portion of the continuous sidewall.

12. An interposer comprising: a base layer including a first surface and a second surface opposite the first surface; a redistribution structure on the first surface of the base layer and including a conductive redistribution pattern; a first lower protection layer on the second surface of the base layer; a lower conductive pad on the first lower protection layer; a through electrode passing through the base layer and the first lower protection layer to electrically connect the conductive redistribution pattern to the lower conductive pad; a second lower protection layer on the first lower protection layer and contacting at least a portion of the lower conductive pad; and an indentation formed in an outer edge region of the interposer to provide a continuous sidewall extending entirely through the second lower protection layer and entirely through the first lower protection layer, wherein the continuous sidewall includes a second curvilinear sidewall extending entirely through the second lower protection layer, a first curvilinear sidewall extending entirely through the first lower protection layer, and a linear sidewall extending between the first curvilinear sidewall and an outer wall of the interposer, and wherein an upper limit of the first curvilinear sidewall is at a vertical level the same as or lower than a vertical level of the second surface of the base layer, the upper limit being measured from (i) an interface between the first lower protection layer and the second lower protection layer toward (ii) an interface between the first lower protection layer and base layer.

13. The interposer of claim 12, wherein the continuous sidewall is smooth without discontinuous transitions.

14. The interposer of claim 12, wherein the second surface of the base layer includes the linear sidewall, and the linear sidewall extends from the first curvilinear sidewall to an outer wall of the interposer.

15. The interposer of claim 12, wherein: the continuous sidewall further includes a third curvilinear sidewall extends through the at least a portion of the base layer, and the linear sidewall extends from the third curvilinear sidewall to the outer wall of the interposer.

16. The interposer of claim 12, wherein: the base layer includes a silicon, the first lower protection layer includes an inorganic material, and the second lower protection layer includes an organic material.