A memory device and method of making the same are disclosed. The memory device includes transistor devices located in both a memory region and a logic region of the device. Transistor devices in the memory region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, a second oxide layer over the first nitride layer, and a second nitride layer over the second oxide layer. Transistor devices in the logic region include sidewall spacers having a first oxide layer over a side surface of a gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor device comprising: a gate structure over a substrate; and a sidewall spacer located on a side surface of the gate structure, the sidewall spacer comprising a first oxide layer over the side surface of the gate structure, a first nitride layer over the first oxide layer, a second oxide over the first nitride layer, and a second nitride layer over the second oxide layer, wherein the first oxide layer extends between a bottom surface of the first nitride layer and the substrate, and the second oxide layer extends between a bottom surface of the second nitride layer and the substrate.
2. The semiconductor device of claim 1, wherein the second oxide layer has a thickness of at least 5 nm.
3. The semiconductor device of claim 1, wherein the substrate comprises a mesa structure, the gate structure is located over an upper surface of the mesa structure and the second oxide layer laterally surrounds the mesa structure.
4. The semiconductor device of claim 3, wherein the first oxide layer extends over the upper surface of the mesa structure between the bottom surface of the first nitride layer and the substrate and contacts the second oxide layer such that the first nitride layer is surrounded on three sides by the first oxide layer and the second oxide layer.
5. The semiconductor device of claim 1, wherein a thickness of the second oxide layer is greater than a thickness of the first oxide layer.
6. The semiconductor device of claim 5, wherein the second oxide layer has a thickness of 20 nm or less.
7. The semiconductor device of claim 6, wherein the first oxide layer has a thickness in a range of 2 nm to 10 nm.
8. The semiconductor device of claim 7, wherein the first nitride layer has a thickness in a range of 5 nm to 15 nm and the second nitride layer has a thickness in a range of 20 nm to 50 nm.
9. The semiconductor device of claim 1, wherein the sidewall spacer is located over two opposite side surfaces of the gate structure.
10. A semiconductor device comprising: a substrate comprising a first mesa structure in a first region of the substrate and a second mesa structure in a second region of the substrate; a first gate structure on the first mesa structure; a second gate structure on the second mesa structure; a first sidewall spacer located on a side surface of the first gate structure, the first sidewall spacer comprising a first oxide layer over the side surface of the first gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer; and a second sidewall spacer located on a side surface of the second gate structure, the second sidewall spacer comprising a first oxide layer over the side surface of the second gate structure, a first nitride layer over the first oxide layer, and a second nitride layer over the first nitride layer, wherein the first mesa structure is laterally surrounded by an oxide material, and the second mesa structure is laterally surrounded by a nitride material.
11. The semiconductor device of claim 10, wherein the first sidewall spacer further comprises a second oxide layer located between the first nitride layer and the second nitride layer along the side surface of the first gate structure and laterally surrounding the first mesa structure.
12. The semiconductor device of claim 11, wherein the second oxide layer extends between the substrate and a lower surface of the second nitride layer of the first sidewall spacer.
13. The semiconductor device of claim 10, wherein the second nitride layer of the second sidewall spacer laterally surrounds the second mesa structure.
14. The semiconductor device of claim 13, wherein the second nitride layer of the second sidewall spacer extends between a lower surface of the first nitride layer of the second sidewall spacer and the substrate.
15. The semiconductor device of claim 10, wherein the second sidewall spacer further comprises a second oxide layer located between the first nitride layer and the second nitride layer along the side surface of the second gate structure, wherein a thickness of the second oxide layer of the second sidewall spacer is 1.5 nm or less.
16. The semiconductor device of claim 15, wherein the first sidewall spacer further comprises a second oxide layer located between the first nitride layer and the second nitride layer along the side surface of the first gate structure, wherein a thickness of the second oxide layer of the first sidewall spacer is at least 5 nm.
17. A method of making a semiconductor device comprising: forming a plurality of gate structures on a substrate, wherein at least one gate structure is formed in a first region of the substrate and at least one gate structure is formed in a second region of the substrate; forming a first oxide layer on a side surface of each of the gate structures; forming a first nitride layer over the first oxide layer on the side surfaces of each of the gate structures; forming a second oxide layer over the first nitride layer on the side surfaces of each of the gate structures; removing the second oxide layer from over the first nitride layer on the side surfaces of each gate structure in the second region of the substrate; and forming a second nitride layer over the second oxide layer on the side surfaces of each of the gate structures in the first region of the substrate, and over the first nitride layer on the side surfaces of each of the gate structures in the second region of the substrate.
18. The method of claim 17, wherein forming the first oxide layer on side surfaces of each of the gate structures and forming the first nitride layer over the first oxide layer on the side surfaces of each of the gate structures further comprises: forming a continuous first oxide layer over the substrate and over the side surfaces and upper surfaces of each of the gate structures; forming a continuous first nitride layer over the first oxide layer; and etching through portions of the continuous first oxide layer, the continuous first nitride layer, and the substrate located between the gate structures to form a plurality of raised mesa structures, each mesa structure including a gate structure located over an upper surface of the mesa structure, a first oxide layer on a side surface of the gate structure and over an upper surface of the mesa structure, and a first nitride layer over the first oxide layer on the side surface of gate structure.
19. The method of claim 18, wherein the second oxide layer is formed over the side surfaces of each of the mesa structures, the second oxide layer is removed from over the side surfaces of the mesa structures in the second region of the substrate, and the second nitride layer is formed over the side surfaces of the mesa structures in the second region of the substrate.
20. The method of claim 18, wherein a portion of the first oxide layer is removed from over an upper surface of the mesa structures in the second region of the substrate, and the second nitride layer is formed between a lower surface of the first nitride layer and the upper surface of the mesa structures in the second region of the substrate.
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May 13, 2024
April 15, 2025
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