Operational instability is prevented without compromising the state transition speed. A mask control circuit is a circuit which generates a mask signal masking a control signal during a period in which a voltage level of a monitoring target terminal to be monitored is transitioning. The mask control circuit includes: a first input port which receives a signal supplied to the monitoring target terminal; a second input port which receives a signal representing the voltage level of the monitoring target terminal; a logic circuit which determines whether the voltage level of the monitoring target terminal is in transition based on signals received from the first input port and the second input port; and an output port which outputs a signal indicating a determination result of whether the voltage level of the monitoring target terminal is in transition as the mask signal.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A mask control circuit generating a mask signal which masks a control signal during a period in which a voltage level of a monitoring target terminal to be monitored is transitioning, the mask control circuit comprising: a second input port receiving a signal also supplied to the monitoring target terminal; a first input port receiving a signal representing the voltage level of the monitoring target terminal; a logic circuit determining whether the voltage level of the monitoring target terminal is in transition based on signals received by the second input port and the first input port; and an output port outputting the mask signal indicating a determination result of whether the voltage level of the monitoring target terminal is in transition.
2. A controller, outputting a control signal which is masked, the controller comprising: a mask control circuit including: a second input port receiving a signal also supplied to a monitoring target terminal to be monitored; a first input port receiving a signal representing a voltage level of the monitoring target terminal; and an output port outputting the control signal indicating a determination result of whether the voltage level of the monitoring target terminal is in transition based on signals received by the second input port and the first input port; and a state transition control circuit including an input port connected to the output port of the mask control circuit and an output port outputting the control signal and which switches to one of a plurality of states, wherein the state transition control circuit is configured to output the control signal which is masked during a period in which the voltage level of the monitoring target terminal is transitioning based on the signal indicating the determination result of whether the voltage level of the monitoring target terminal is in transition.
3. A charge/discharge control circuit which controls charge/discharge of a secondary battery, the charge/discharge control circuit comprising: a positive power supply terminal and a negative power supply terminal for monitoring a voltage of the secondary battery; a charge control terminal connected to a gate of a charge control FET which controls charge of the secondary battery; a discharge control terminal connected to a gate of a discharge control FET which controls discharge of the secondary battery; an external negative voltage input port receiving, among an external positive electrode terminal and an external negative electrode terminal to which either a charger charging the secondary battery or a load discharging the secondary battery is connected, a voltage of the external negative electrode terminal; a monitoring circuit monitoring a voltage of the monitoring target terminal, comprising at least the charge control terminal and the external negative voltage input port among terminals included in the charge/discharge control circuit, and generating a signal representing a voltage level of the monitoring target terminal and a signal representing a state of the charge/discharge control circuit based on a monitoring result; and the controller according to claim 2, wherein the controller has a state transition function for transitioning between an on state in which a predetermined function is exerted and an off state in which the predetermined function is stopped, and a charge control FET on/off control function and a discharge control FET on/off control function for switching between an on state and an off state of the charge control FET and the discharge control FET, determines whether the voltage level of the monitoring target terminal is in transition based on the signal representing the voltage level of the monitoring target terminal and a signal supplied to the monitoring target terminal while switching between the on state and the off state of the charge control FET and the discharge control FET based on the monitoring result, and temporarily prohibits a state transition between the on state and the off state of the predetermined function when determining that the voltage level of the monitoring target terminal is in transition.
4. The charge/discharge control circuit according to claim 3, wherein the monitoring target terminal comprises the charge control terminal.
5. The charge/discharge control circuit according to claim 3, wherein the monitoring target terminal comprises the discharge control terminal.
6. The charge/discharge control circuit according to claim 3, wherein the controller comprises a FET control circuit which generates a charge control signal for switching and controlling on and off of the charge control FET and a discharge control signal for switching and controlling on and off of the discharge control FET, and supplies the charge control signal to the gate of the charge control FET and supplies the discharge control signal to the gate of the discharge control FET, the state transition control circuit comprises a power-down control circuit which supplies to the FET control circuit a control signal for transitioning between a power-down state in which a power-down function for reducing current consumption inside the charge/discharge control circuit is exerted when an overdischarged state of the charge/discharge control circuit is detected, and a power-down release state in which the power-down function is stopped, and the mask control circuit determines whether a voltage level of the charge control terminal is in transition based on the charge control signal and a signal representing the voltage level of the charge control terminal, generates a mask signal which is a signal corresponding to a determination result and represents whether to mask an on state of the control signal, and supplies the mask signal to the power-down control circuit.
7. The charge/discharge control circuit according to claim 6, wherein the power-down control circuit comprises an input port receiving a signal representing a temperature protection state in which a temperature protection function for stopping at least one of charge and discharge outside a predetermined temperature range is exerted, and a temperature protection release state in which the temperature protection function is stopped, and supplies to the FET control circuit the control signal for transitioning to the power-down state in the temperature protection state and transitioning to the power-down release state in the temperature protection release state.
8. The charge/discharge control circuit according to claim 6, wherein the power-down control circuit comprises an input port receiving a signal representing an on state of a charge control FET protection function in which the charge control FET protection function for turning off the charge control FET is exerted in a charge overcurrent state, and an off state of the charge control FET protection function for stopping the charge control FET protection function and turning on the charge control FET, and supplies to the FET control circuit the control signal for transitioning to the power-down state in the on state of the charge control FET protection function and transitioning to the power-down release state in the off state of the charge control FET protection function.
9. A battery device, comprising: the charge/discharge control circuit according to claim 3; the secondary battery; the external positive electrode terminal and the external negative electrode terminal; the charge control FET provided in a charge/discharge path connecting the external positive electrode terminal and the external negative electrode terminal via the secondary battery; and the discharge control FET provided in the charge/discharge path.
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December 8, 2021
April 15, 2025
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