Delay circuit and memory

1. A delay circuit, comprising: a self-shielding circuit, configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N−1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases; and a delay, electrically connected to the self-shielding circuit, and configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal; wherein the self-shielding circuit comprises: a shielding circuit, configured to receive the N initial clock signals and output N intermediate clock signals; wherein the N intermediate clock signals comprise a first intermediate clock signal that is valid and N−1 second intermediate clock signals that are invalid; and a register, electrically connected to the shielding circuit, and configured to: receive the initial command signal and the N intermediate clock signals, register the initial command signal according to the first intermediate clock signal, and obtain and output the N intermediate command signals.

2. The delay circuit of claim 1, wherein the register comprises N self-shielding triggers, each of the N self-shielding triggers is a D flip-flop, and the N intermediate command signals comprise a first intermediate command signal that is valid and N−1 second intermediate command signals that are invalid; wherein a first input end of each of the N self-shielding triggers is configured to receive the initial command signal, and a second input end of each of the N self-shielding triggers is connected to an output end of the shielding circuit; wherein a first self-shielding trigger among the N self-shielding triggers that receives the first intermediate clock signal is configured to register the initial command signal according to the first intermediate clock signal, and a first output end of the first self-shielding trigger is configured to output the first intermediate command signal; and wherein other N−1 second self-shielding triggers among the N self-shielding triggers are configured to receive the N−1 second intermediate clock signals at one-to-one correspondence, and first output ends of the N−1 second self-shielding triggers are configured to output the N−1 second intermediate command signals at one-to-one correspondence.

3. The delay circuit of claim 2, wherein the shielding circuit comprises N AND gates, and each of the N AND gates comprises a first input end and N−1 second input ends; wherein first input ends of the N AND gates are configured to receive the N initial clock signals at one-to-one correspondence, and output ends of the N AND gates are connected to second input ends of the N self-shielding triggers at one-to-one correspondence; and wherein for each of the N AND gates, the N−1 second input ends of the N AND gate are respectively connected to second output ends of N−1 self-shielding triggers other than a self-shielding trigger corresponding to the AND gate.

4. The delay circuit of claim 2, wherein the shielding circuit comprises N inverters and N NOR gates, and each of the NOR gates comprises a first input end and N−1 second input ends; wherein input ends of the N inverters are configured to receive the N initial clock signals at one-to-one correspondence, output ends of the N inverters are connected to first input ends of the N NOR gates at one-to-one correspondence, and output ends of the N NOR gates are connected to the second input ends of the N self-shielding triggers at one-to-one correspondence; and wherein for each of the N NOR gates, the N−1 second input ends of the N NOR gate are connected to first output ends of N−1 self-shielding triggers other than a self-shielding trigger corresponding to the NOR gate.

5. The delay circuit of claim 2, wherein the delay comprises M stages of second registers, M being an integer greater than or equal to 2; each of the M stages of second registers comprises N delay triggers, and each of the N delay triggers is a D flip-flop; wherein second input ends of the N delay triggers in each of the M stages of second registers are configured to receive the N initial clock signals at one-to-one correspondence; wherein first input ends of N delay triggers in a first stage of second register are connected to first output ends of the N self-shielding triggers at one-to-one correspondence; and wherein first input ends of the N delay triggers in an ith stage of second register are respectively connected to output ends of N delay triggers in a stage of second register immediately previous to the ith stage of second register, and i is greater than 1 and less than or equal to M.

6. The delay circuit of claim 5, wherein M=(CL−A)/N, CL is a maximum number of delay periods, and A is a number of periods corresponding to a command pre-operation.

7. The delay circuit of claim 5, wherein the delay further comprises an OR gate, and the OR gate comprises N input ends; and wherein first output ends of the N delay triggers in an Mth stage of second register are connected to the N input ends of the OR gate at one-to-one correspondence, and an output end of the OR gate is configured to output the delayed command signal.

8. The delay circuit of claim 1, wherein N=2, the N initial clock signals are odd-even frequency division clock signals, and the odd-even frequency division clock signals comprise an odd clock signal and an even clock signal; wherein the odd clock signal has a same frequency as the even clock signal, and has a phase opposite to a phase of the even clock signal.

9. The delay circuit of claim 8, wherein the register comprises a first self-shielding trigger and a second self-shielding trigger, and each of the first self-shielding trigger and the second self-shielding trigger is a D flip-flop; and wherein a first input end of the first self-shielding trigger and a first input end of the second self-shielding trigger are configured to receive the initial command signal.

10. The delay circuit of claim 9, wherein the shielding circuit comprises a first AND gate and a second AND gate, and each of the first AND gate and the second AND gate has two input ends; wherein a first input end of the first AND gate is configured to receive the even clock signal, an output end of the first AND gate is connected to a second input end of the first self-shielding trigger, and a second input end of the first AND gate is connected to a second output end of the second self-shielding trigger; and wherein a first input end of the second AND gate is configured to receive the odd clock signal, an output end of the second AND gate is connected to a second input end of the second self-shielding trigger, and a second input end of the second AND gate is connected to a second output end of the first self-shielding trigger.

11. The delay circuit of claim 9, wherein the shielding circuit comprises a first inverter, a second inverter, a first NOR gate and a second NOR gate, and each of the first NOR gate and the second NOR gate has two input ends; wherein an input end of the first inverter is configured to receive the even clock signal, and an output end of the first inverter is connected to a first input end of the first NOR gate; wherein an output end of the first NOR gate is connected to a second input end of the first self-shielding trigger, and a second input end of the first NOR gate is connected to a first output end of the second self-shielding trigger; wherein an input end of the second inverter is configured to receive the odd clock signal, and an output end of the second inverter is connected to a first input end of the second NOR gate; and wherein an output end of the second NOR gate is connected to a second input end of the second self-shielding trigger, and a second input end of the second NOR gate is connected to a first output end of the first self-shielding trigger.

12. A memory comprising a delay circuit, the delay circuit comprises: a self-shielding circuit, configured to: receive an initial command signal and N initial clock signals, register the initial command signal according to a first initial clock signal among the N initial clock signals that triggers the initial command signal at earliest, shield other N−1 second initial clock signals among the N initial clock signals, and output N intermediate command signals, where N is an integer greater than or equal to 2, and the N initial clock signals have a same frequency and different phases; and a delay, electrically connected to the self-shielding circuit, and configured to: receive the N intermediate command signals and the N initial clock signals, and delay and output the N intermediate command signals to obtain a delayed command signal; and wherein the self-shielding circuit comprises: a shielding circuit, configured to receive the N initial clock signals and output N intermediate clock signals; wherein the N intermediate clock signals comprise a first intermediate clock signal that is valid and N−1 second intermediate clock signals that are invalid; and a register, electrically connected to the shielding circuit, and configured to: receive the initial command signal and the N intermediate clock signals, register the initial command signal according to the first intermediate clock signal, and obtain and output the N intermediate command signals.

13. The memory of claim 12, wherein the register comprises N self-shielding triggers, each of the N self-shielding triggers is a D flip-flop, and the N intermediate command signals comprise a first intermediate command signal that is valid and N−1 second intermediate command signals that are invalid; wherein a first input end of each of the N self-shielding triggers is configured to receive the initial command signal, and a second input end of each of the N self-shielding triggers is connected to an output end of the shielding circuit; wherein a first self-shielding trigger among the N self-shielding triggers that receives the first intermediate clock signal is configured to register the initial command signal according to the first intermediate clock signal, and a first output end of the first self-shielding trigger is configured to output the first intermediate command signal; and wherein other N−1 second self-shielding triggers among the N self-shielding triggers are configured to receive the N−1 second intermediate clock signals at one-to-one correspondence, and first output ends of the N−1 second self-shielding triggers are configured to output the N−1 second intermediate command signals at one-to-one correspondence.

14. The memory of claim 13, wherein the shielding circuit comprises N AND gates, and each of the N AND gates comprises a first input end and N−1 second input ends; wherein first input ends of the N AND gates are configured to receive the N initial clock signals at one-to-one correspondence, and output ends of the N AND gates are connected to second input ends of the N self-shielding triggers at one-to-one correspondence; and wherein for each of the N AND gates, the N−1 second input ends of the N AND gate are respectively connected to second output ends of N−1 self-shielding triggers other than a self-shielding trigger corresponding to the AND gate.

15. The memory of claim 13, wherein the shielding circuit comprises N inverters and N NOR gates, and each of the NOR gates comprises a first input end and N−1 second input ends; wherein input ends of the N inverters are configured to receive the N initial clock signals at one-to-one correspondence, output ends of the N inverters are connected to first input ends of the N NOR gates at one-to-one correspondence, and output ends of the N NOR gates are connected to the second input ends of the N self-shielding triggers at one-to-one correspondence; and wherein for each of the N NOR gates, the N−1 second input ends of the N NOR gate are connected to first output ends of N−1 self-shielding triggers other than a self-shielding trigger corresponding to the NOR gate.

16. The memory of claim 13, wherein the delay comprises M stages of second registers, M being an integer greater than or equal to 2; each of the M stages of second registers comprises N delay triggers, and each of the N delay triggers is a D flip-flop; wherein second input ends of the N delay triggers in each of the M stages of second registers are configured to receive the N initial clock signals at one-to-one correspondence; wherein first input ends of N delay triggers in a first stage of second register are connected to first output ends of the N self-shielding triggers at one-to-one correspondence; and wherein first input ends of the N delay triggers in an ith stage of second register are respectively connected to output ends of N delay triggers in a stage of second register immediately previous to the ith stage of second register, and i is greater than 1 and less than or equal to M.

17. The memory of claim 12, wherein N=2, the N initial clock signals are odd-even frequency division clock signals, and the odd-even frequency division clock signals comprise an odd clock signal and an even clock signal; wherein the odd clock signal has a same frequency as the even clock signal, and has a phase opposite to a phase of the even clock signal.

18. The memory of claim 12, wherein the memory is electrically connected to a controller, the memory satisfies a 4th-generation double data rate (DDR4) specification, and the controller satisfies a 5th-generation double data rate (DDR5) specification; and the memory further comprises a frequency division circuit; wherein the memory is configured to receive a standard clock signal from the controller, divide the standard clock signal into the initial clock signals through the frequency division circuit, and transmit the initial clock signals to the delay circuit.