SRAM with backside cross-couple

1. An SRAM device comprising: a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; and a backside cross-couple at the backside underneath the first and second PD transistors, the backside cross-couple connecting a first source/drain (S/D) region of the second PD transistor with a gate of the first PD transistor.

2. The SRAM device of claim 1, further comprising a first internal contact shared by a first S/D region of the first PU transistor and a first S/D region of the first PD transistor, and a frontside cross-couple at the frontside above the first and second PU transistors, the frontside cross-couple connecting the first internal contact with a gate of the second PU transistor.

3. The SRAM device of claim 2, further comprising a second internal contact shared by a first S/D region of the second PU transistor and the first S/D region of the second PD transistor.

4. The SRAM device of claim 3, wherein a first S/D region of a first pass-gate (PG) transistor shares the first internal contact with the first PU transistor and the first PD transistor, and a first S/D region of a second PG transistor shares the second internal contact with the second PU transistor and the second PD transistor.

5. The SRAM device of claim 3, wherein the backside cross-couple connects the second internal contact with the gate of the first PD transistor.

6. The SRAM device of claim 1, wherein the first PU transistor and the first PD transistor share a first common gate, and the second PU transistor and the second PD transistor share a second common gate.

7. The SRAM device of claim 1, further comprising a set of VDD power supply lines connected to a second S/D region of the first and second PU transistors at the frontside, and a set of VSS power supply lines connected to a second S/D region of the first and second PD transistors at the backside.

8. A method of forming an SRAM device comprising: forming a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor and a second PU transistor stacked over a second PD transistor; and forming a backside cross-couple underneath the first and second PD transistors connecting a first source/drain (S/D) region of the second PD transistor with a gate of the first PD transistor.

9. The method of claim 8, further comprising forming a first internal contact shared by a first S/D region of the first PU transistor and a first S/D region of the first PD transistor and forming a second internal contact shared by a first S/D region of the second PU transistor and the first S/D region of the second PD transistor.

10. The method of claim 9, further comprising forming a frontside cross-couple above the first and second PU transistors connecting the first S/D region of the first PU transistor with a gate of the second PU transistor.

11. The method of claim 10, further comprising forming contacts to second source/drain regions of the first PU transistor, the second PU transistor, a first pass-gate (PG) transistor, and a second PG transistor; and forming a set of bit lines and a set of VDD power supply lines above the first and second PU transistors.

12. The method of claim 11, further comprising forming a set of back-end-of-line (BEOL) layers over the set of bit lines and the set of VDD power supply lines and bonding a carrier wafer to the BEOL layers.

13. The method of claim 12, wherein, before forming the backside cross-couple, the first and second PD transistors are formed on a buried oxide layer over a semiconductor substrate, further comprising flipping the carrier wafer, removing the semiconductor substrate to expose the buried oxide layer, and forming contacts to the first and second PD transistors.

14. The method of claim 13, further comprising forming a set of VSS power supply lines connecting to a second S/D region of the first and second PD transistors.

15. The method of claim 14, further comprising forming backside power distribution network (BSPDN) above the set of VSS power supply lines.

16. An SRAM memory comprising: a frontside and a backside; a first pull-up (PU) transistor stacked over a first pull-down (PD) transistor; a second PU transistor stacked over a second PD transistor; a frontside cross-couple at the frontside above the first and second PU transistors, the frontside cross-couple connecting a first source/drain (S/D) region of the first PU transistor with a gate of the second PU transistor; and a backside cross-couple at the backside underneath the first and second PD transistors, the backside cross-couple connecting a first S/D region of the second PD transistor with a gate of the first PD transistor.

17. The SRAM memory of claim 16, further comprising a first internal contact shared by the first S/D region of the first PU transistor and a first S/D region of the first PD transistor, a second internal contact shared by a first S/D region of the second PU transistor and the first S/D region of the second PD transistor, wherein the frontside cross-couple connects to the first S/D region of the first PU transistor via the first internal contact.

18. The SRAM memory of claim 17, wherein the backside cross-couple connects to the second internal contact shared by the first S/D region of the second PD transistor.

19. The SRAM memory of claim 17, wherein a first S/D region of a first pass-gate (PG) transistor shares the first internal contact with the first PU transistor and the first PD transistor, and a first S/D region of a second PG transistor shares the second internal contact with the second PU transistor and the second PD transistor.

20. The SRAM memory of claim 16, further comprising a set of VDD power supply lines connecting to a second S/D region of the first and second PU transistors at the frontside, and a set of VSS power supply lines connecting to a second S/D region of the first and second PD transistors at the backside.