A resistive random-access memory (RRAM) circuit includes a current source configured to output a first current, a first n-type transistor including a first drain terminal configured to receive the first current, an RRAM device, second and third n-type transistors including respective second and third drain terminals coupled to an output terminal of the RRAM device, an amplifier including a non-inverting input coupled to the first drain terminal, an inverting input configured to receive a first reference voltage level, and an output coupled to a gate of each of the first through third n-type transistors, a fourth n-type transistor coupled between the second n-type transistor and a power supply reference node, and a comparator including a non-inverting input configured to receive a second reference voltage level, an inverting input coupled to each of the second and third drain terminals, and an output coupled to a gate of the fourth n-type transistor.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A resistive random-access memory (RRAM) circuit comprising: a current source configured to output a first current; a first n-type transistor comprising a first drain terminal configured to receive the first current; an RRAM device; second and third n-type transistors comprising respective second and third drain terminals coupled to an output terminal of the RRAM device; an amplifier comprising a non-inverting input coupled to the first drain terminal, an inverting input configured to receive a first reference voltage level, and an output coupled to a gate of each of the first through third n-type transistors; a fourth n-type transistor coupled between the second n-type transistor and a power supply reference node; and a comparator comprising a non-inverting input configured to receive a second reference voltage level, an inverting input coupled to each of the second and third drain terminals, and an output coupled to a gate of the fourth n-type transistor.
2. The RRAM circuit of claim 1, wherein the RRAM device comprises a variable resistance structure coupled to the output terminal, the variable resistance structure comprising a resistive layer.
3. The RRAM circuit of claim 2, wherein the RRAM device further comprises a switching device coupled in series with the variable resistance structure.
4. The RRAM circuit of claim 1, wherein the first, second, and third n-type transistors have dimensions configured to cause a sum of currents through the second and third n-type transistors to be equal to the first current.
5. The RRAM circuit of claim 1, wherein the second and third n-type transistors have dimensions configured to cause a current through the second n-type transistor to be less than a current through the third n-type transistor.
6. The RRAM circuit of claim 1, wherein the comparator is configured to output a first signal comprising a first transition from a high logical state to a low logical state responsive to a voltage at the inverting input rising above the second reference voltage level.
7. The RRAM circuit of claim 1, wherein the current source is configured to output the first current having a current level ranging from 50 microamperes (μA) to 500 μA.
8. The RRAM circuit of claim 1, wherein one or both of the first or second reference voltage levels is equal to approximately 0.1 volts.
9. The RRAM circuit of claim 1, wherein the RRAM device is a first RRAM device, the comparator is a first comparator, and the RRAM circuit further comprises: a second RRAM device; fifth and sixth n-type transistors comprising respective fourth and fifth drain terminals coupled to an output terminal of the second RRAM device; a seventh n-type transistor coupled between the fifth n-type transistor and the power supply reference node; and a second comparator comprising a non-inverting input configured to receive the second reference voltage level, an inverting input coupled to each of the fourth and fifth drain terminals, and an output coupled to a gate of the seventh n-type transistor, wherein the amplifier output is further coupled to a gate of each of the fifth and sixth n-type transistors.
10. A resistive random-access memory (RRAM) circuit comprising: a current source configured to output a first current; a first n-type transistor comprising a first drain terminal configured to receive the first current; an RRAM device; second and third n-type transistors comprising respective second and third drain terminals coupled to an output terminal of the RRAM device; an amplifier comprising a non-inverting input coupled to the first drain terminal, an inverting input configured to receive a first reference voltage level, and an output coupled to a gate of each of the first through third n-type transistors; a fourth n-type transistor coupled between the second n-type transistor and a power supply reference node; a fifth n-type transistor coupled between the third n-type transistor and the power supply reference node; a delay element comprising an output terminal coupled to a gate of the fifth n-type transistor; and a comparator comprising a non-inverting input configured to receive a second reference voltage level, an inverting input coupled to each of the second and third drain terminals, and an output coupled to a gate of the fourth n-type transistor and an input terminal of the delay element.
11. The RRAM circuit of claim 10, wherein the delay element further comprises: a series of inverters coupled to the input terminal; and an OR gate coupled to the output terminal, wherein the OR gate comprises: a first input terminal coupled to the input terminal of the delay element; and a second input terminal coupled to the series of inverters.
12. The RRAM circuit of claim 11, wherein the comparator is configured to output a first signal comprising a first transition from a high logical state to a low logical state responsive to a voltage at the inverting input rising above the second reference voltage level, and the OR gate and the series of inverters are configured to output a second signal comprising a second transition from the high logical state to the low logical state responsive to the first transition.
13. The RRAM circuit of claim 12, wherein the OR gate and the series of inverters are configured to output the second transition delayed from the first transition by a period ranging from 100 nanoseconds (ns) to 1000 ns.
14. The RRAM circuit of claim 10, wherein the second and third n-type transistors have dimensions configured to cause a current through the second n-type transistor to be the same as a current through the third n-type transistor.
15. The RRAM circuit of claim 10, wherein the first and second reference voltage levels are a same reference voltage level.
16. A resistive random-access memory (RRAM) circuit comprising: a current source and a first n-type transistor coupled in series between a power supply node and a power supply reference node, wherein the current source is configured to output a first current to a first drain terminal of the first n-type transistor; an RRAM device coupled to a bit line through a selection circuit; second and third n-type transistors comprising respective second and third drain terminals coupled to an output terminal of the RRAM device; an amplifier comprising a non-inverting input coupled to the first drain terminal, an inverting input configured to receive a first reference voltage level, and an output coupled to a gate of each of the first through third n-type transistors; a fourth n-type transistor coupled between the second n-type transistor and the power supply reference node; and a comparator comprising a non-inverting input configured to receive a second reference voltage level, an inverting input coupled to each of the second and third drain terminals, and an output coupled to a gate of the fourth n-type transistor.
17. The RRAM circuit of claim 16, further comprising: a fifth n-type transistor coupled in series with the current source and the first transistor, wherein a gate of the fifth transistor is configured to receive a logic signal.
18. The RRAM circuit of claim 17, wherein the fifth n-type transistor is coupled between the first transistor and the power supply reference node.
19. The RRAM circuit of claim 16, wherein the selection circuit comprises a p-type transistor configured to receive a selection signal.
20. The RRAM circuit of claim 16, wherein the selection circuit comprises a multiplexer.
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March 25, 2024
May 20, 2025
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