Display apparatus and method of controlling the same

1. A display apparatus comprising: a display; a video processor configured to process a video signal and comprising a video scaler; a graphic processor configured to process a graphic signal; a mixer configured to mix a video corresponding to the video signal processed by the video processor and a graphic corresponding to the graphic signal processed by the graphic processor to be displayed together on the display; and a main processor configured to: identify a video frame among a plurality of video frames matching a graphic frame among a plurality of graphic frames, based on identification information assigned to the plurality of video frames of the video signal and identification information assigned to the plurality of graphic frames of the graphic signal, control the video processor and/or the graphic processor to delay output of at least one of the identified video frame and the identified graphic frame to make the video comprising the identified video frame and the graphic of the identified graphic frame be displayed together on the display, control the identified video frame and the identified graphic frame to be synchronized and output by the video processor and the graphic processor at a reference point in time set based on a predetermined sync signal, set geometry information to display the video corresponding to the video signal by executing an application, and provide the set geometry information to the video scaler, the geometry information including at least one of size information of the video or position information of the video.

2. The display apparatus of claim 1, wherein a frame rate of the video signal is different from a frame rate of the graphic signal.

3. The display apparatus of claim 1, wherein the main processor is configured to assign the identification information to the plurality of video frames in sequence, assign the identification information to the plurality of graphic frames in sequence, and identify the video frame and the graphic frame to which the matching identification information is assigned.

4. The display apparatus of claim 1, wherein the main processor is configured to control data of the video frames to be sequentially stored in a first queue at least by assigning the identification information to the plurality of video frames, control data of the graphic frames to be sequentially stored in a second queue at least by assigning the identification information to the plurality of graphic frames, and control the data of the video frame and the data of the graphic frame, to which the matching identification information is assigned, to be respectively output from the first queue and the second queue at a reference point in time set based on a predetermined sync signal.

5. The display apparatus of claim 4, further comprising a frame rate converter configured to convert a frame rate of the video signal, wherein the main processor is configured to identify a delay time that occurs during conversion of the frame rate, and control the data of the identified graphic frame between at least the video frame and the graphic frame, to which the matching identification information is assigned, to be output as being more delayed by the identified delay time than the data of the identified video frame.

6. The display apparatus of claim 1, further comprising: a frame rate converter configured to convert a frame rate of the video signal; and a memory unit comprising a buffer configured to store the graphic signal processed by the graphic processor based on a delay time that occurs during conversion of the frame rate.

7. The display apparatus of claim 1, wherein the graphic processor comprises a graphic scaler, and the main processor is configured to render the graphic corresponding to the graphic signal at least by executing an application, setting a pointer identifying a start point and an end point to output the rendered graphic, and providing information about the set pointer to the graphic scaler.

8. The display apparatus of claim 1, further comprising a memory unit comprising a first buffer configured to store the video signal processed by the video processor, and a second buffer configured to store the graphic signal processed by the graphic processor, wherein the main processor is configured to control the video of the video frame of the video signal stored in the first buffer, and the graphic of the graphic frame of the graphic signal stored in the second buffer to be synchronized and output.

9. The display apparatus of claim 2, wherein the predetermined sync signal comprises a vertical sync signal for the display.

10. A display apparatus comprising: a display; a video processor configured to process a video signal; a graphic processor configured to process a graphic signal and comprising a graphic scaler; a mixer configured to mix a video corresponding to the video signal processed by the video processor and a graphic corresponding to the graphic signal processed by the graphic processor to be displayed together on the display; and a main processor configured to: identify a video frame among a plurality of video frames matching a graphic frame among a plurality of graphic frames, based on identification information assigned to the plurality of video frames of the video signal and identification information assigned to the plurality of graphic frames of the graphic signal, control the video processor and/or the graphic processor to delay output of at least one of the identified video frame and the identified graphic frame to make the video comprising the identified video frame and the graphic of the identified graphic frame be displayed together on the display, control the identified video frame and the identified graphic frame to be synchronized and output by the video processor and the graphic processor at a reference point in time set based on a predetermined sync signal, and render the graphic corresponding to the graphic signal at least by executing an application, setting a pointer identifying a start point and an end point to output the rendered graphic, and providing information about the set pointer to the graphic scaler.

11. The display apparatus of claim 10, wherein the graphics processor comprises a video scaler, and the main processor is configured to set geometry information to display the video corresponding to the video signal by executing an application, and provide the set geometry information to the video scaler, the geometry information including at least one of size information of the video or position information of the video.

12. The display apparatus of claim 10, wherein a frame rate of the video signal is different from a frame rate of the graphic signal.

13. A method of controlling a display apparatus comprising video processor configured to process a video signal and a graphic processor configured to process a graphic signal, the method comprising: identifying a video frame among a plurality of video frames matching a graphic frame among a plurality of graphic frames, based on identification information assigned to the plurality of video frames of the video signal and identification information assigned to the plurality of graphic frames of the graphics signal; controlling the video processor and/or the graphic processor to delay output of at least one of the identified video frame and the identified graphic frame to make a video comprising the identified video frame and a graphic of the identified graphic frame be displayed together on a display; controlling the identified video frame and the identified graphic frame to be synchronized and output by the video processor and the graphic processor at a reference point in time set based on a predetermined sync signal; setting geometry information to display the video corresponding to the video signal by executing an application, and providing the set geometry information to a video scaler included in the video processor, the geometry information including at least one of size information of the video or position information of the video.

14. The method of claim 13, wherein a frame rate of the video signal is different from a frame rate of the graphic signal.

15. The method of claim 13, further comprising assigning the identification information to the plurality of video frames in sequence, and assigning the identification information to the plurality of graphic frames in sequence.

16. The method of claim 13, further comprising: storing data of the video frames sequentially in a first queue at least by assigning the identification information to the plurality of video frames; storing data of the graphic frames sequentially in a second queue at least by assigning the identification information to the plurality of graphic frames; and controlling the data of the video frame and the data of the graphic frame, to which the matching identification information is assigned, to be respectively output from the first queue and the second queue at a reference point in time set based on a predetermined sync signal.

17. The method of claim 13, further comprising: identifying a delay time that occurs during frame rate conversion of a video signal; and controlling data of the identified graphic frame between the video frame and the graphic frame, to which the matching identification information is assigned, to be output as being more delayed by the identified delay time than data of the identified video frame.