Semiconductor packages having connecting structure

1. A semiconductor package comprising: a substrate including an upper pad at a top surface of the substrate; a semiconductor chip on the substrate and including a chip pad at a top surface of the semiconductor chip, wherein the chip pad is electrically connected to the upper pad via a first wire; a connecting structure on the semiconductor chip and including a connecting pad and a probe pad at a top surface of the connecting structure, wherein the connecting pad is electrically connected to the probe pad via a third wire, and the connecting pad is electrically connected to the upper pad via a second wire; an encapsulant covering and in direct contact with each of the substrate, the semiconductor chip, and the connecting structure; and a test terminal on the connecting structure and extending through the encapsulant, the test terminal being electrically connected to and in direct contact with the probe pad of the connecting structure; wherein the connecting structure electrically interconnects the semiconductor chip and the test terminal via a signal path that passes from the test terminal to the probe pad of the connecting structure, from the probe pad of the connecting structure to the connecting pad of the connecting structure via the third wire, from the connecting pad of the connecting structure to the upper pad of the substrate via the second wire, and from the upper pad of the substrate to the chip pad of the semiconductor chip via the first wire.

2. The semiconductor package according to claim 1, wherein: a horizontal width of the connecting structure is smaller than a horizontal width of the semiconductor chip; and the connecting structure does not overlap with the chip pad in a vertical direction.

3. The semiconductor package according to claim 1, wherein an upper end of the test terminal is disposed vertically at a higher level than a top surface of the encapsulant.

4. The semiconductor package according to claim 3, wherein a top surface of the test terminal is rounded.

5. The semiconductor package according to claim 1, wherein the connecting pad contacts a bottom surface of the test terminal.

6. The semiconductor package according to claim 1, wherein: the encapsulant includes a through hole in which the test terminal is disposed; and an inner wall of the through hole is partially exposed.

7. The semiconductor package according to claim 6, wherein an upper end of the test terminal is disposed vertically at a lower level than a top surface of the encapsulant.

8. The semiconductor package according to claim 1, wherein: a side surface of the connecting structure and a side surface of the semiconductor chip are coplanar; and a horizontal width of the connecting structure is equal to a horizontal width of the semiconductor chip.

9. The semiconductor package according to claim 1, wherein the semiconductor chip is a memory chip.

10. A semiconductor package comprising: a lower package, and an upper package on the lower package, wherein the upper package includes: an upper substrate including an upper pad at a top surface of the upper substrate, a package connecting terminal at a bottom surface of the upper substrate, an upper semiconductor chip on the upper substrate and including a chip pad at a top surface of the upper semiconductor chip, wherein the chip pad is electrically connected to the upper pad via a first wire, a connecting structure on the upper semiconductor chip and including a connecting pad and a probe pad at a top surface of the connecting structure, wherein the connecting pad is electrically connected to the probe pad via a third wire, and the connecting pad is and electrically connected to the upper pad via a second wire, an upper encapsulant covering and in direct contact with each of the upper substrate, the upper semiconductor chip, and the connecting structure, and a test terminal on the connecting structure and extending through the upper encapsulant, the test terminal being electrically connected to and in direct contact with the probe pad of the connecting structure; wherein the lower package includes: a first lower substrate, a lower semiconductor chip on the first lower substrate, and a second lower substrate on the first lower substrate and the lower semiconductor chip and connected to the upper package by the package connecting terminal, wherein the connecting structure electrically interconnects the upper semiconductor chip and the test terminal via a signal path that passes from the test terminal to the probe pad of the connecting structure, from the probe pad of the connecting structure to the connecting pad of the connecting structure via the third wire, from the connecting pad of the connecting structure to the upper pad of the upper substrate via the second wire, and from the upper pad of the upper substrate to the chip pad of the semiconductor chip via the first wire.

11. The semiconductor package according to claim 10, further comprises: a conductive pillar interconnecting the first lower substrate and the second lower substrate.

12. The semiconductor package according to claim 10, further comprising: a connecting member interconnecting the first lower substrate and the second lower substrate, wherein the connecting member includes base layers and conductive vias extending through the base layers.

13. The semiconductor package according to claim 10, wherein: the upper semiconductor chip includes a memory chip; and the lower semiconductor chip includes a logic chip.

14. A semiconductor package comprising: a substrate including an upper pad at a top surface of the substrate; an outer connecting terminal at a bottom surface of the substrate; a semiconductor chip disposed on the substrate and including a chip pad at a top surface of the semiconductor chip, wherein the chip pad is electrically connected to the upper pad via a first wire interconnecting the chip pad and the upper pad; a first adhesive between the substrate and the semiconductor chip; a connecting structure on the semiconductor chip and including a connecting pad and a probe pad at a top surface of the connecting structure, wherein the connecting pad is electrically connected to the probe pad via a third wire, and the connecting pad is electrically connected to the upper pad via a second wire interconnecting the connecting pad and the upper pad; a second adhesive between the semiconductor chip and the connecting structure; an encapsulant covering and in direct contact with each of the substrate, the semiconductor chip, and the connecting structure; and a test terminal on the connecting structure and extending through the encapsulant, the test terminal being electrically connected to and in direct contact with the probe pad of the connecting structure; wherein the test terminal protrudes upwardly to a higher level than a top surface of the encapsulant, wherein the connecting structure electrically interconnects the semiconductor chip and the test terminal via a signal path that passes from the test terminal to the probe pad of the connecting structure, from the probe pad of the connecting structure to the connecting pad of the connecting structure via the third wire, from the connecting pad of the connecting structure to the upper pad of the substrate via the second wire, and from the upper pad of the substrate to the chip pad of the semiconductor chip via the first wire.