A semiconductor package structure includes a semiconductor die, at least one wiring structure, a metal support, a passive element, a plurality of signal vias, and a plurality of thermal structures. The semiconductor die has an active surface. The at least one wiring structure is electrically connected to the active surface of the semiconductor die. The metal support is used for supporting the semiconductor die. The passive element is electrically connected to the semiconductor die. The signal vias are electrically connecting the passive element and the semiconductor die. The thermal structures are connected to the passive element, and the thermal structures are disposed on a periphery of the at least one wiring structure.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A semiconductor package structure, comprising: a passive element including a main body, an electrode and a metal pin spaced apart from the electrode, wherein the electrode is configured to transmit a signal from the main body, and the metal pin is configured to transmit a heat generated by the main body and includes a first portion and a base portion connected to the first portion and wider than the first portion; and a dielectric layer disposed between the electrode and the metal pin, wherein the dielectric layer is spaced apart from a portion of the electrode, the base portion is substantially level with the electrode, and a width of the electrode is less than a width of the base portion of the metal pin.
2. The semiconductor package structure of claim 1, further comprising a signal circuit electrically connected to the electrode and a thermal structure thermally connected to the metal pin, wherein the thermal structure is spaced apart from the signal circuit.
3. The semiconductor package structure of claim 2, wherein the thermal structure includes a thermal layer, the base portion of the metal pin includes a first region directly contacting the thermal layer and a second region not contacting the thermal layer, and a width of the first region is greater than a width of the second region.
4. The semiconductor package structure of claim 3, wherein a width of the thermal layer is less than a width of the metal pin.
5. The semiconductor package structure of claim 4, wherein the thermal structure further includes a plurality of thermal vias directly contacting the thermal layer.
6. The semiconductor package structure of claim 1, further comprising a thermal structure thermally connected to the metal pin and including a plurality of thermal vias arranged in a two-dimensional array.
7. The semiconductor package structure of claim 1, further comprising a plurality of signal vias electrically connected to the passive element and comprising a plurality of thermal vias thermally connected to the metal pin, wherein in a top view, a total number of the plurality of thermal vias is greater than a total number of the plurality of signal vias.
8. The semiconductor package structure of claim 1, further comprising a plurality of thermal vias thermally connected to the metal pin to transmit the heat from the main body, wherein the plurality of thermal vias are entirely disposed within a vertical projection of the metal pin.
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February 11, 2021
June 3, 2025
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