Data receiving circuit, data receiving system and memory device

1. A data receiving circuit, comprising: a first amplifier circuit configured to receive a data signal, a first reference signal and a second reference signal, perform a first comparison between the data signal and the first reference signal and output a first signal pair as a result of the first comparison, perform a second comparison between the data signal and the second reference signal, and output a second signal pair as a result of the second comparison; wherein a level value of the first reference signal is different from a level value of the second reference signal, the first signal pair comprising a first signal and a second signal, and the second signal pair comprising a third signal and a fourth signal; and a second amplifier circuit configured to select to receive the first signal pair or the second signal pair as input signal pairs based on a feedback signal, amplify a voltage difference between the input signal pairs, and output a first output signal and a second output signal as a result of the amplification, wherein the feedback signal is obtained based on previously received data; and, wherein the second amplifier circuit comprises: a first input subcircuit connected to a seventh node and an eighth node, the first input subcircuit being configured to be turned on in response to the feedback signal to receive the first signal pair and compare the first signal pair, and respectively provide a signal to the seventh node and the eighth node; a second input subcircuit connected to the seventh node and the eighth node, the second input subcircuit being configured to be turned on in response to the feedback signal to receive the second signal pair and compare the second signal pair, and provide a signal to the seventh node and the eighth node, respectively, wherein either of the first input subcircuit and the second input subcircuit is selectively turned on based on the feedback signal; and a latch subcircuit connected to the seventh node and the eighth node, the latch subcircuit being configured to amplify and latch a signal of the seventh node and a signal of the eighth node, and output the first output signal and the second output signal respectively through a first output node and a second output node.

2. The data receiving circuit of claim 1, wherein the first amplifier circuit comprises: a first comparison circuit having a first node and a second node, the first comparison circuit being configured to receive the data signal and the first reference signal and perform the first comparison, and output the first signal and the second signal respectively through the first node and the second node; and a second comparison circuit having a third node and a fourth node, the second comparison circuit being configured to receive the data signal and the second reference signal and perform the second comparison, and output the third signal and the fourth signal respectively through the third node and the fourth node.

3. The data receiving circuit of claim 2, wherein the first comparison circuit comprises: a first current source connected between a power supply node and a fifth node, the first current source being configured to provide a current to the fifth node in response to a sampling clock signal; and a first comparison subcircuit connected to the first node, the second node and the fifth node, the first comparison subcircuit being configured to receive the data signal and the first reference signal, perform the first comparison when the first current source provides the current to the fifth node, and output the first signal and the second signal; the second comparison circuit comprises: a second current source connected between the power supply node and a sixth node, the second current source being configured to provide a current to the sixth node in response to the sampling clock signal; and a second comparison subcircuit connected to the third node, the fourth node and the sixth node, the second comparison subcircuit being configured to receive the data signal and the second reference signal, perform the second comparison when the second current source provides the current to the sixth node, and output the third signal and the fourth signal.

4. The data receiving circuit of claim 3, wherein a circuit structure of the first current source is the same as a circuit structure of the second current source; and a circuit structure of the first comparison subcircuit is the same as a circuit structure of the second comparison subcircuit.

5. The data receiving circuit of claim 3, wherein the first current source comprises: a first PMOS transistor connected between the power supply node and the fifth node, a gate of the first PMOS transistor being configured to receive the sampling clock signal; wherein the second current source comprises: a second PMOS transistor connected between the power supply node and the sixth node, a gate of the second PMOS transistor being configured to receive the sampling clock signal.

6. The data receiving circuit of claim 3, wherein the first comparison subcircuit comprises: a third PMOS transistor connected between the first node and the fifth node, a gate of the third PMOS transistor being configured to receive the data signal; and a fourth PMOS transistor connected between the second node and the fifth node, a gate of the fourth PMOS transistor being configured to receive the first reference signal; wherein the second comparison subcircuit comprises: a fifth PMOS transistor connected between the third node and the sixth node, a gate of the fifth PMOS transistor being configured to receive the data signal; and a sixth PMOS transistor connected between the fourth node and the sixth node, a gate of the sixth PMOS transistor being configured to receive the second reference signal.

7. The data receiving circuit of claim 3, wherein the first amplifier circuit further comprises: a first reset subcircuit connected to the first node and the second node, the first reset subcircuit being configured to reset the first node and the second node; and a second reset subcircuit connected to the third node and the fourth node, the second reset subcircuit being configured to reset the third node and the fourth node.

8. The data receiving circuit of claim 7, wherein the first reset subcircuit comprises: a first NMOS transistor connected between the first node and a ground terminal, a gate of the first NMOS transistor being configured to receive a first reset signal; a second NMOS transistor connected between the second node and the ground terminal, a gate of the second NMOS transistor being configured to receive the first reset signal; wherein the second reset subcircuit comprises: a third NMOS transistor connected between the third node and the ground terminal, a gate of the third NMOS transistor being configured to receive the first reset signal; and a fourth NMOS transistor connected between the fourth node and the ground terminal, a gate of the fourth NMOS transistor being configured to receive the first reset signal.

9. The data receiving circuit of claim 1, wherein the feedback signal comprises a differential first feedback signal and a second feedback signal, the first input subcircuit being turned on in response to the first feedback signal, and the second input subcircuit being turned on in response to the second feedback signal.

10. The data receiving circuit of claim 9, wherein the first input subcircuit comprises: a fifth NMOS transistor and a sixth NMOS transistor, a drain of the fifth NMOS transistor being connected to the seventh node, a source of the fifth NMOS transistor being connected to a drain of the sixth NMOS transistor, a source of the sixth NMOS transistor being connected to a ground terminal, a gate of the fifth NMOS transistor being configured to receive one of the first signal or the first feedback signal, and a gate of the sixth NMOS transistor being configured to receive other one of the first signal or the first feedback signal; and a seventh NMOS transistor and an eighth NMOS transistor, a drain of the seventh NMOS transistor being connected to the eighth node, a source of the seventh NMOS transistor being connected to a drain of the eighth NMOS transistor, a source of the eighth NMOS transistor being connected to the ground terminal, a gate of the seventh NMOS transistor being configured to receive one of the second signal or the first feedback signal, and a gate of the eighth NMOS transistor being configured to receive other one of the second signal or the first feedback signal.

11. The data receiving circuit of claim 9, wherein the second input subcircuit comprises: a ninth NMOS transistor and a tenth NMOS transistor, a drain of the ninth NMOS transistor being connected to the seventh node, a source of the ninth NMOS transistor being connected to a drain of the tenth NMOS transistor, and a source of the tenth NMOS transistor being connected to the ground terminal; wherein a gate of the ninth NMOS transistor is configured to receive one of the third signal or the second feedback signal, a gate of the tenth NMOS transistor being configured to receive either one of the third signal or the second feedback; and an eleventh NMOS transistor and a twelfth NMOS transistor, a drain of the eleventh NMOS transistor being connected to the eighth node, a source of the eleventh NMOS transistor being connected to a drain of the twelfth NMOS transistor, and a source of the twelfth NMOS transistor being connected to the ground terminal; wherein a gate of the eleventh NMOS transistor is configured to receive one of the fourth signal or the second feedback signal, a gate of the twelfth NMOS transistor being configured to receive other one of the fourth signal or the second feedback signal.

12. The data receiving circuit of claim 1, wherein the latch subcircuit comprises: a thirteenth NMOS transistor and a seventh PMOS transistor, a gate of the thirteenth NMOS transistor and a gate of the seventh PMOS transistor being both connected to the second output node, a source of the thirteenth NMOS transistor being connected to the seventh node, a drain of the thirteenth NMOS transistor and a drain of the seventh PMOS transistor being both connected to the first output node, and a source of the seventh PMOS transistor being connected to a power supply node; and a fourteenth NMOS transistor and an eighth PMOS transistor, a gate of the fourteenth NMOS transistor and a gate of the eighth PMOS transistor being both connected to the first output node, a source of the fourteenth NMOS transistor being connected to the eighth node, a drain of the fourteenth NMOS transistor and a drain of the eighth PMOS transistor being both connected to the second output node, and a source of the eighth PMOS transistor being connected to the power supply node.

13. The data receiving circuit of claim 1, wherein the second amplifier circuit further comprises: a third reset subcircuit connected between a power supply node and an output terminal of the latch subcircuit, the third reset subcircuit being configured to reset the output terminal of the latch subcircuit.

14. The data receiving circuit of claim 13, wherein the output terminal of the latch subcircuit comprises a first output node and a second output node; and the third reset subcircuit comprises: a ninth PMOS transistor connected between the first output node and the power supply node, a gate of the ninth PMOS transistor being configured to receive a second reset signal; and a tenth PMOS transistor connected between the second output node and the power supply node, a gate of the tenth PMOS transistor being configured to receive the second reset signal.

15. A data receiving system, comprising: a plurality of cascaded data transmission circuits, each of the plurality of data transmission circuits comprising the data receiving circuit according to claim 1 and a latch circuit connected to the data receiving circuit; wherein an output signal from the data transmission circuit at a previous stage is used as the feedback signal of the data transmission circuit at a next stage; and an output signal from the data transmission circuit at a last stage is used as the feedback signal of the data transmission circuit at a first stage.

16. The data receiving system of claim 15, wherein the data receiving circuit is configured to receive data in response to a sampling clock signal; and the data receiving system comprises four cascaded data receiving circuits, a phase difference of the sampling clock signal of the data receiving circuit at adjacent stages being 90°.

17. The data receiving system of claim 15, wherein the feedback signal of the data transmission circuit at the next stage is an output signal from the data receiving circuit at a previous stage or an output signal from the latch circuit at a previous stage; and the feedback signal of the data transmission circuit at the first stage is an output signal from the data receiving circuit at a last stage or an output signal from the latch circuit at a last stage.

18. A memory device, comprising a plurality of data ports; and a plurality of data receiving systems as claimed in claim 15, each of the plurality of data receiving systems corresponding to one of the plurality of data ports.