Embodiments provide a semiconductor structure and fabrication method. The method include: forming sacrificial layers on a sidewall of the first pattern mask layer and a sidewall of the second pattern mask layer, and forming a first filling layer filling a first spacing between the sacrificial layers; removing the first filling layer, the first pattern mask layer and the second pattern mask layer, retaining the sacrificial layers and the first spacing, and replacing a second spacing between the first pattern mask layer and the second pattern mask layer; forming a second filling layer filling the first spacing and the second spacing; etching the sacrificial layers based on the second filling layer to form etched patterns, and etching the pattern transfer layer and the target layer based on the etched patterns to form a first pattern target layer in the array region and a second pattern target layer in the peripheral region.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate comprising an array region and a peripheral region; forming a target layer covering a top of the substrate and a pattern transfer layer covering the target layer; forming a first pattern mask layer and a second pattern mask layer, the first pattern mask layer being positioned on a surface of the pattern transfer layer at a top of the array region, and the second pattern mask layer being positioned on the surface of the pattern transfer layer at a top of the peripheral region, wherein a pattern dimension of the first pattern mask layer is smaller than a pattern dimension of the second pattern mask layer, and a pattern density of the first pattern mask layer is greater than a pattern density of the second pattern mask layer: forming sacrificial layers and a first filling layer, the sacrificial layers at least covering a sidewall of the first pattern mask layer and a sidewall of the second pattern mask layer, and the first filling layer filling a first spacing between the sacrificial layers; removing the first filling layer, the first pattern mask layer and the second pattern mask layer, retaining the sacrificial layers and the first spacing, and replacing a second spacing between the first pattern mask layer and the second pattern mask layer; forming a second filling layer, the second filling layer filling the first spacing and the second spacing, and a top surface of the second filling layer being flush with top surfaces of the sacrificial layers; etching the sacrificial layers based on the second filling layer to form etched patterns, and etching the pattern transfer layer based on the etched patterns; and transferring the etched patterns to the target layer along the pattern transfer layer etched, to form, on a surface of the target layer, a first pattern positioned directly above the array region and a second pattern positioned directly above the peripheral region.
2. The method for fabricating the semiconductor structure according to claim 1, wherein a ratio of a thickness of the sacrificial layer positioned on the sidewall of the first pattern mask layer to a width of the sidewall of the first pattern mask layer ranges from 1:2 to 1:10.
3. The method for fabricating the semiconductor structure according to claim 1, wherein a width of the first spacing positioned directly above the array region is equal to a width of the second spacing.
4. The method for fabricating the semiconductor structure according to claim 1, wherein the forming the first pattern mask layer and the second pattern mask layer comprises: forming a mask layer, the mask layer covering a top surface of the pattern transfer layer; forming a first pattern photoresist on the mask layer, and patterning, based on the first pattern photoresist, the mask layer positioned directly above the array region to form the first pattern mask layer; and forming a second pattern photoresist on the mask layer, and patterning, based on the second pattern photoresist, the mask layer positioned directly above the peripheral region to form the second pattern mask layer.
5. The method for fabricating the semiconductor structure according to claim 1, wherein the forming the sacrificial layers and the first filling layer comprises: forming initial sacrificial layers, wherein the initial sacrificial layers cover a top surface and the sidewall of the first pattern mask layer and the top surface of the pattern transfer layer exposed by the first pattern mask layer, and cover a top surface and the sidewall of the second pattern mask layer and the top surface of the pattern transfer layer exposed by the second pattern mask layer; forming an initial first filling layer, the initial first filling layer filling a spacing between the initial sacrificial layers and covering top surfaces of the initial sacrificial layers; and removing the initial sacrificial layers by part of a height and the initial first filling layer by part of a height to expose the top surface of the first pattern mask layer and the top surface of the second pattern mask layer, a remaining part of the initial sacrificial layers being defined as the sacrificial layers, and a remaining part of the initial first filling layer being defined as the first filling layer.
6. The method for fabricating the semiconductor structure according to claim 5, wherein after forming the initial sacrificial layers and before forming the initial first filling layer, the method further comprises: removing the initial sacrificial layers on the top surface of the first pattern mask layer and the top surface of the second pattern mask layer and the initial sacrificial layer positioned on the surface of the pattern transfer layer; and wherein the forming the initial first filling layer further comprises: the initial first filling layer covering the surface of the pattern transfer layer and the top surface of the first pattern mask layer and the top surface of the second pattern mask layer.
7. The method for fabricating the semiconductor structure according to claim 5, wherein the removing the initial sacrificial layers by part of the height and the initial first filling layer by part of the height comprises: removing the initial first filling layer by part of the height to expose the initial sacrificial layers positioned on the top surface of the first pattern mask layer and the top surface of the second pattern mask layer; and removing the initial sacrificial layers on the top surface of the first pattern mask layer and the top surface of the second pattern mask layer.
8. The method for fabricating the semiconductor structure according to claim 1, wherein the pattern transfer layer comprises a hard mask layer and a transfer sub-layer, the transfer sub-layer covering the surface of the target layer, and the hard mask layer covering a surface of the transfer sub-layer.
9. The method for fabricating the semiconductor structure according to claim 1, wherein the forming the second filling layer comprises: forming an initial second filling layer, the initial second filling layer filling the first spacing and the second spacing, and a top surface of the initial second filling layer being higher than the top surfaces of the sacrificial layers; and removing the initial second filling layer by part of a height to expose the top surfaces of the sacrificial layers.
10. The method for fabricating the semiconductor structure according to claim 9, wherein the forming the initial second filling layer comprises: a height difference between a top surface of the initial second filling layer positioned above the array region and the top surface of the initial second filling layer positioned above the peripheral region being less than 5 nm.
11. The method for fabricating the semiconductor structure according to claim 1, wherein a process for forming the sacrificial layers comprises: a chemical vapor deposition process, a physical vapor deposition process, or an atomic layer deposition process.
12. The method for fabricating the semiconductor structure according to claim 1, wherein a material for forming the sacrificial layers comprises silicon oxide.
13. The method for fabricating the semiconductor structure according to claim 1, wherein a process for forming the first filling layer and a process for the second filling layer both comprise: a spin-on carbon process.
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September 26, 2022
June 17, 2025
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