A method of failure analysis for locating open circuit defect in a metal layers, comprising: providing a chip sample having a metal layer, with an open circuit defect; delaminating the chip to expose the metal layer; depositing a metal conductive layer on the metal layer; removing a portion of the metal conductive layer to expose the metal layer; depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer; preparing a TEM slice sample which comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer; performing a VC analysis on the TEM slice sample to determine the defect position of the open circuit defect; and analyzing the defect position of the open circuit defect.
Legal claims defining the scope of protection, as filed with the USPTO.
1. A failure analysis method for locating a defect position, comprising following steps: step 1, providing a chip sample having a metal layer, wherein the metal layer has an open circuit defect; step 2, delaminating the chip sample to expose a top surface of the metal layer having the open circuit defect; step 3, depositing a metal conductive layer on the metal layer of the chip sample; step 4, removing a portion of the metal conductive layer from a top surface the metal layer to expose the metal layer; step 5, depositing a non-conductive protective layer to cover the exposed metal layer and any remaining portions of the metal conductive layer of the chip sample; step 6, preparing a TEM (Transmission Electron Microscopy) slice sample from the chip sample, wherein the TEM slice sample comprises the metal layer, the remaining portions of the metal conductive layer, and the non-conductive protective layer; step 7, performing a VC (voltage contrast) analysis on the TEM slice sample to determine the defect position of the open circuit defect; and step 8, analyzing the defect position of the open circuit defect on the TEM slice sample.
2. The failure analysis method for locating the defect position according to claim 1, wherein the metal conductive layer is deposited by means of a FIB (focused ion beam) in step 3.
3. The failure analysis method for locating the defect position according to claim 1, wherein the portion of the metal conductive layer on the metal layer is removed by means of a FIB in step 4.
4. The failure analysis method for locating the defect position according to claim 1, wherein the non-conductive protective layer is deposited by means of a FIB in step 5.
5. The failure analysis method for locating the defect position according to claim 4, wherein the non-conductive protective layer in step 5 is a carbon protective layer.
6. The failure analysis method for locating the defect position according to claim 1, wherein the TEM slice sample is prepared by means of a FIB in step 6.
7. The failure analysis method for locating the defect position according to claim 1, wherein the VC analysis is performed on the TEM slice sample by means of a FIB in step 7.
8. The failure analysis method for locating the defect position according to claim 1, wherein the defect position of the open circuit defect on the TEM slice sample is analyzed by means of the TEM in step 8.
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February 16, 2023
June 24, 2025
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