Display substrate, manufacturing method thereof and display apparatus

The present application is a U.S. National Phase Entry of International Application No. PCT/CN2022/108886 having an international filing date of Jul. 29, 2022, the content of which is incorporated into this application by reference.

The present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display substrate, a manufacturing method thereof and a display apparatus.

Micro organic light emitting diodes (Micro OLEDs) are micro displays developed in recent years, among which a silicon-based OLED is one type thereof. The silicon-based OLED can implement not only active addressing of pixels, but also manufacturing of structures such as pixel driving circuits on a silicon base, so as to facilitate reduction of system volume to implement lightweight. The silicon-based OLED, which is manufactured using mature complementary metal oxide semiconductor (CMOS) integrated circuit technologies, has advantages such as a small size, a high pixels per inch (PPI), a high refresh rate, etc.

The following is a summary of subject matters described in the present disclosure in detail. The summary is not intended to limit the protection scope of the claims.

In one aspect, an embodiment of the present disclosure provides a display substrate including a display area and a border area. The display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, a sub-pixel includes a first region, a gap region and a second region arranged in sequence along a pixel row direction; at least one sub-pixel includes a pixel driving circuit, a first scan signal line and a second scan signal line, the pixel driving circuit at least includes a first transistor, a second transistor and a third transistor, the first scan signal line is configured to control turning-on or turning-off of the first transistor, and the second scan signal line is configured to control turning-on or turning-off of the second transistor; the first transistor at least includes a first gate electrode, a first active layer, a first electrode and a second electrode of the first transistor, the second transistor at least includes a second gate electrode and a second active layer, and the third transistor at least includes a third gate electrode and a third active layer; the first active layer is disposed in the first region, the second active layer and the third active layer are disposed in the second region, and the second active layer is disposed at one side of the third active layer in a pixel column direction; the first scan signal line is connected to the first gate electrode through a first gate via hole, the second electrode of the first transistor is connected to the second gate electrode through a second gate via hole, the second scan signal line is connected to the third gate electrode through a third gate via hole, and the first gate via hole, the second gate via hole and the third gate via hole are provided in the gap region.

In an exemplary embodiment, along the pixel row direction, the first region has a first width, the second region has a second width, and the gap region has a third width, the third width is less than or equal to 0.5*the first width, and the third width is less than or equal to 0.5*the second width.

In an exemplary embodiment, first gate electrodes of two adjacent sub-pixels in a pixel row are connected to each other to form an integrated structure, and third gate electrodes of two adjacent sub-pixels in a pixel row are connected to each other to form an integrated structure.

In an exemplary embodiment, the first gate electrodes of the integrated structure are connected to the first scan signal line through two first gate via holes, and the third gate electrodes of the integrated structure are connected to the second scan signal line through two third gate via holes.

In an exemplary embodiment, first transistors, second transistors and third transistors of two adjacent sub-pixels in a pixel row are mirror symmetrical with respect to a pixel centerline, which is a straight line located between the two adjacent sub-pixels in a pixel row and extending along the pixel column direction.

In an exemplary embodiment, in at least one sub-pixel, the first gate electrode includes a first gate body portion and a first gate connection portion connected to each other, the first gate connection portion is disposed in the gap region, and the first scan signal line is connected to the first gate connection portion through the first gate via hole.

In an exemplary embodiment, in at least one sub-pixel, the second gate electrode includes a second gate body portion and a second gate connection portion connected to each other, the second gate connection portion is disposed in the gap region, and the second electrode of the first transistor is connected to the second gate connection portion through the second gate via hole.

In an exemplary embodiment, in at least one sub-pixel, the third gate electrode includes a third gate body portion and a third gate connection portion connected to each other, the third gate connection portion is disposed in the gap region, and the second scan signal line is connected to the third gate connection portion through the third gate via hole.

In an exemplary embodiment, in at least one sub-pixel, the first gate electrode includes a first gate body portion and a first gate connection portion connected to each other, the first gate connection portion is disposed at one side of the first gate body portion close to the third gate electrode, and the third gate electrode includes a third gate body portion and a third gate connection portion connected to each other, the third gate connection portion is disposed at one side of the third gate body portion close to the first gate electrode, and the first gate connection portion and the third gate connection portion are interlaced in the pixel column direction.

In an exemplary embodiment, an edge of the first gate body portion and an edge of the first gate connection portion that are away from the second transistor are flush, and an edge of the third gate body portion and an edge of the third gate connection portion that are close to the second transistor are flush.

In an exemplary embodiment, in at least one sub-pixel, the second gate electrode includes a second gate body portion and a second gate connection portion connected to each other, the second gate connection portion is disposed in the gap region, and an edge of the second gate body portion and an edge of the second gate connection portion that are close to the third transistor are flush.

In an exemplary embodiment, a main part of the first scan signal line and a main part of the second scan signal line are in a shape of a line extending along the pixel row direction, an orthographic projection of the first scan signal line on a plane of the display substrate overlaps at least partially with orthographic projections of the first gate electrode and the third gate electrode on the plane of the display substrate, and an orthographic projection of the second scan signal line on the plane of the display substrate overlaps at least partially with the orthographic projections of the first gate electrode and the third gate electrode on the plane of the display substrate.

In an exemplary embodiment, the second transistor further includes a first electrode and a second electrode of the second transistor, and the third transistor further includes a first electrode and a second electrode, the first electrode of the first transistor is connected to a data signal line, the first electrode of the second transistor is connected to a light emitting voltage line, the first electrode of the third transistor is connected to a reference signal line, and the second electrode of the second transistor and the second electrode of the third transistor are connected to each other to form an integrated structure.

In an exemplary embodiment, in at least one sub-pixel, the pixel driving circuit further includes a storage capacitor including a first plate and a second plate, an orthographic projection of the first plate on a plane of the display substrate overlapping at least partially with an orthographic projection of the second plate on the plane of the display substrate, the first plate is connected to the second electrode of the first transistor through a connection electrode, and the second plate is connected to a first power supply line.

In an exemplary embodiment, at least one sub-pixel further includes a contact electrode disposed in the first region, the contact electrode is disposed at one side of the first active layer in the pixel column direction.

In an exemplary embodiment, at least one sub-pixel further includes a bias voltage line connected to the contact electrode through a via hole, an orthographic projection of the bias voltage line on a plane of the display substrate overlapping at least partially with an orthographic projection of the second gate electrode on the plane of the display substrate.

In an exemplary embodiment, in at least one sub-pixel, the contact electrode is in a shape of a strip extending along the pixel column direction, the bias voltage line is in a shape of a line extending along the pixel row direction, a bias connection line is connected at one or both sides of the bias voltage line in the pixel column direction, an orthographic projection of the bias connection line on the plane of the display substrate overlaps at least partially with an orthographic projection of the contact electrode on the plane of the display substrate, and the bias connection line is connected to the contact electrode through a via hole.

In an exemplary embodiment, the bias voltage line and the bias connection line are connected to each other to form an integrated structure.

In an exemplary embodiment, the border area at least includes a light emitting control transistor, a gate electrode of the light emitting control transistor is connected to a light emitting control line, a first electrode of the light emitting control transistor is connected to a border power supply lead, a second electrode of the light emitting control transistor is connected to the light emitting voltage line, which is connected to first electrodes of second transistors of a plurality of sub-pixels in a pixel row, and the border power supply lead is connected to the first power supply line.

In an exemplary embodiment, in a plane perpendicular to the display substrate, the display substrate at least includes a first conductive layer and a second conductive layer disposed in sequence on a silicon base, the silicon base at least includes the first active layer, the second active layer and the third active layer, the first conductive layer at least includes the first gate electrode, the second gate electrode and the third gate electrode, and the second conductive layer at least includes the first scan signal line and the second scan signal line.

In an exemplary embodiment, the display substrate further includes a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer and an eighth conductive layer disposed on one side of the second conductive layer away from the silicon base, the third conductive layer at least includes a data signal line and a reference signal line, the fourth conductive layer at least includes a light emitting voltage line, the sixth conductive layer at least including a first plate of a storage capacitor, the seventh conductive layer at least includes a second plate of the storage capacitor, and the eighth conductive layer at least includes an anode connection electrode and a first power supply line.

In another aspect, an example of the present disclosure provides a display apparatus, which includes the aforementioned display substrate.

In yet another aspect, an example of the present disclosure provides a manufacturing method of a display substrate including a display area and a border area, wherein the display area includes a plurality of sub-pixels forming pixel rows and pixel columns, a sub-pixel includes a first region, a gap region and a second region arranged in sequence along a pixel row direction; at least one sub-pixel includes a pixel driving circuit, a first scan signal line and a second scan signal line, the pixel driving circuit at least includes a first transistor, a second transistor and a third transistor, the first scan signal line is configured to control turning-on or turning-off of the first transistor, and the second scan signal line is configured to control turning-on or turning-off of the second transistor; the first transistor at least includes a first gate electrode, a first active layer, a first electrode and a second electrode of the first transistor, the second transistor at least includes a second gate electrode and a second active layer, and the third transistor at least includes a third gate electrode and a third active layer; the manufacturing method includes:

Other aspects may become clear after the accompanying drawings and the detailed description are read and understood.

In order to make objects, technical schemes and advantages of the present disclosure more clear, embodiments of the present disclosure will be described below in detail in combination with the drawings. It should be noted that embodiments may be implemented in a number of different forms. Those of ordinary skills in the art may readily understand the fact that implementations and contents may be transformed into various forms without departing from the essence and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents recorded in following embodiments only. The embodiments in the present disclosure and features in the embodiments may be arbitrarily combined with each other without conflicts. In order to keep the following description of the embodiments of the present disclosure clear and concise, detailed descriptions of a portion of known functions and known components are omitted in the present disclosure. The drawings in the embodiments of the present disclosure relate only to the structures involved in the embodiments of the present disclosure, and conventional designs may be used as references for other structures.

Scales of the drawings in the present disclosure may be used as references in the actual processes, but are not limited thereto. For example, a width-to-length ratio of a channel, a thickness of each film layer and a spacing between two film layers, and a width of each signal line and a spacing between two signal lines may be adjusted according to actual needs. The number of pixels in a display apparatus and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings. The drawings described in the present disclosure are schematic structure diagrams only, and one implementation of the present disclosure is not limited to the shapes or numerical values shown in the drawings.

Ordinal numerals such as “first”, “second”, “third” and the like in the specification are set in order to avoid confusion of the constituent elements, but not set to make a limit in quantity.

For convenience, the terms such as “middle”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside” and the like indicating orientation or position relationships are used in the specification to illustrate position relationships between the constituent elements with reference to the drawings, and are intended to facilitate description of the specification and simplification of the description, but not to indicate or imply that the mentioned device or element must have a specific orientation or be constructed and operated in a specific orientation, therefore, they should not be understood as limitations to the present disclosure. The position relationships between the constituent elements are appropriately changed according to directions of the constituent elements described. Therefore, words and phrases used in the specification are not limited and appropriate substitutions may be made according to situations.

Unless otherwise specified and defined explicitly, the terms “install”, “couple” and “connect” should be understood in a broad sense in the specification. For example, the connection may be a fixed connection, a detachable connection or an integrated connection, or may be a mechanical connection or an electrical connection, or may be a direct connection, an indirect connection through an intermediate component, or communication inside two components. The specific meanings of the above terms in the present disclosure may be understood by a person of ordinary skills in the art according to the specific situations.

In the specification, a transistor refers to a component which at least includes three terminals, that is, a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain) and the source electrode (source electrode terminal, source region or source), and a current can flow through the drain electrode, the channel region and the source electrode. It should be noted that in the specification, the channel region refers to a region which a current flows mainly through.

In the specification, in order to distinguish between two electrodes of the transistor except the gate electrode, one of the two electrodes is directly referred to as a first electrode and the other is referred to as a second electrode. The first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case that transistors with opposite polarities are used or the case that a current direction is changed during circuit operation, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, in the specification, the “source electrode” and the “drain electrode” may be interchangeable.

In the specification, “electrical connection” includes a case where the constituent elements are connected together through an element with a certain electrical effect. The “element with the certain electrical effect” is not particularly limited as long as electrical signals may be sent and received between the connected constituent elements. Examples of the “element with the certain electrical action” not only include an electrode and a wiring, but also include a switching element (such as a transistor), a resistor, an inductor, a capacitor, other elements with one or more functions, etc.

In the specification, “parallel” refers to a state in which an angle formed by two straight lines is −10° or greater than −10° and 100 or less than 10°, and thus also includes a state in which the angle is −5° or greater than −5° and 5° or less than 5°. In addition, “vertical” refers to a state in which an angle formed by two straight lines is 800 or greater than 800 and 1000 or less than 100°, and thus also includes a state in which the angle is 850 or greater than 850 and 950 or less than 95°.

In the specification, “film” and “layer” may be interchangeable. For example, sometimes “conductive layer” may be replaced by “conductive film”. Similarly, sometimes “insulating film” may be replaced by “insulating layer”.

“Being disposed on the same layer” mentioned in the specification means that two (or more than two) structures are formed by patterning through the same patterning process, and they may be made of the same or different materials. For example, materials of the precursors forming a plurality of structures disposed on the same layer are the same, and the resulting materials may be the same or different.

Triangle, rectangle, trapezoid, pentagon or hexagon in the specification are not in the strict sense, and they may be approximate triangle, rectangle, trapezoid, pentagon or hexagon, in which there may be some small deformations caused by tolerance, or there may be chamfers, arc edges and deformation, etc.

“About” in the present disclosure means that a boundary is defined loosely and numerical values in process and measurement error ranges are allowed.

is a schematic diagram of a structure of a display apparatus of a silicon-based OLED. As shown in, the display apparatus of the silicon-based OLED may include a time sequence controller, a data signal driver, a scan signal driver and a pixel array. The pixel array may include a plurality of scan signal lines (Sto Sm), a plurality of data signal lines (Dto Dn) and a plurality of sub-pixels Pxij. In an exemplary embodiment, the time sequence controller may provide grayscale values and control signals suitable for the specification of the data signal driver to the data signal driver, and provide clock signals and scan start signals suitable for the specification of the scan signal driver to the scan signal driver. The data signal driver may generate data voltages to be provided to the data signal lines D, D, D, . . . , and Dn using the grayscale values and the control signals that are received from the time sequence controller. For example, the data signal driver may sample the grayscale values using the clock signals and apply the data voltages corresponding to the grayscale values to the data signal lines Dto Dn by taking a row of sub-pixels as a unit, wherein n may be a natural number. The scan signal driver may generate scan signals to be provided to the scan signal lines S, S, S, . . . , and Sm by receiving the clock signals and the scan start signals from the time sequence controller. For example, the scan signal driver may sequentially provide scan signals with on-level pulses to the scan signal lines Sto Sm. For example, the scan signal driver may be constructed in the form of a shift register and generate the scan signals by sequentially transmitting the scan start signals provided in the form of on-level pulses to a next-stage circuit under the control of the clock signal, wherein m may be a natural number. The sub-pixel array may include a plurality of sub-pixels PXij. Each sub-pixel PXij may be connected to a corresponding data signal line and a corresponding scan signal line, wherein i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which a transistor is connected to both the i-th scan signal line and the j-th data signal line.

is a schematic planar structure diagram of a display apparatus of a silicon-based OLED. As shown in, the display apparatus may include a plurality of pixel units P arranged in a matrix, at least one of the plurality of pixel units P includes a first sub-pixel Pemitting light of a first color, a second sub-pixel Pemitting light of a second color and a third sub-pixel Pemitting light of a third color. The three sub-pixels each include a pixel driving circuit and a light emitting device. The pixel driving circuit in the sub-pixel is connected to the scan signal line and the data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line, and output a corresponding current to the display light emitting device. The display light emitting device in the sub-pixel is connected to the pixel driving circuit of the sub-pixel where the display light emitting device is located, and is configured to emit light with corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the display light-emitting device is located.

In an exemplary embodiment, the first sub-pixel Pmay be a red (R) sub-pixel emitting red light, the second sub-pixel Pmay be a blue (B) sub-pixel emitting blue light, and the third sub-pixel Pmay be a green (G) sub-pixel emitting green light.

In an exemplary embodiment, the sub-pixels may be in the shape of any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon and other polygons. The three sub-pixels may be arranged side by side horizontally, side by side vertically or in a shape of the Chinese character “”, and the present disclosure is not limited thereto. In some other possible embodiments, the pixel unit may include four sub-pixels, and the present disclosure is not limited thereto.

is a schematic section structure diagram of a display apparatus of a silicon-based OLED, which illustrates a structure in which full color is implemented in a manner of white light+color filter. As shown in, the display apparatus of the silicon-based OLED may include a silicon base, a driving circuit layerdisposed on the silicon base, a light emitting structure layerdisposed on one side of the driving circuit layeraway from the silicon base, a first encapsulation layerdisposed on one side of the light emitting structure layeraway from the silicon base, a color filter structure layerdisposed on one side of the first encapsulation layeraway from the silicon base, a second encapsulation layerdisposed on one side of the color filter structure layeraway from the silicon base, and a cover plate layerdisposed on one side of the second encapsulation layeraway from the silicon base. In some possible implementations, the display apparatus of the silicon-based OLED may include other film layers, and the present disclosure is not limited thereto.

In an exemplary embodiment, the silicon basemay be a bulk silicon base or a silicon-on-insulator (SOI) substrate. The driving circuit layermay be fabricated on the silicon basethrough a silicon semiconductor process (e.g., a CMOS process). The driving circuit layermay include a plurality of circuit units, a circuit unit may at least include a pixel driving circuit connected to a scan signal line and a data signal line, respectively. The pixel driving circuit may include a plurality of transistor and a storage capacitor. One transistor is shown only inas an example. The transistor may include a gate electrode G, a first electrode S and a second electrode D. The gate electrode G, the first electrode S and the second electrode D may be electrically connected respectively to the corresponding connection electrodes through via holes filled with wolfram metal (i.e., wolfram via, W-via), and may be connected to other electrical structures (e.g., traces) through the connection electrodes.

In an exemplary embodiment, the light emitting structure layermay include a plurality of light emitting devices, and a light emitting device may at least include an anode, an organic light emitting layer and a cathode. The anode may be connected to the second electrode D of the transistor through a connection electrode, the organic light emitting layer is connected to the anode, the cathode is connected to the organic light emitting layer, and the cathode is connected to a second power supply line. The organic light emitting layer emits light under the driving of the anode and the cathode. In an exemplary embodiment, the organic light emitting layer may include an emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron block layer (EBL), a hole block layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL). In an exemplary embodiment, for a light emitting device emitting white light, the organic light emitting layers of all sub-pixels may be connected together to form a common layer.

In an exemplary embodiment, the first encapsulation layerand the second encapsulation layermay adopt a manner of thin film encapsulation (TFE), so as to ensure that external water vapor cannot enter the light emitting structure layer. The cover plate layermay be made of glass, or plastic colorless polyimide having flexible characteristics, or the like.