Memory cell array of a static random access memory and a static random access memory including the same

This application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0003326 filed on Jan. 10, 2023 in the Korean Intellectual Property Office (KIPO), the disclosure of which is incorporated by reference herein in its entirety.

Example embodiments of the present disclosure relate generally to semiconductor integrated circuits, and more particularly to memory cell arrays of static random access memories, and static random access memories including the memory cell arrays.

As miniaturization technology advances, transistors are made smaller, necessitating voltage scaling to ensure reliability and manage power consumption. However, this miniaturization process amplifies the impact of variations in manufacturing parameters. Consequently, the threshold voltages of transistors in memory cells become increasingly variable, reducing the operation margin of the memory. This makes it challenging to perform stable reading and writing with a low power supply voltage.

Various configurations have been proposed to ensure stable data writing and reading in a static random access memory (SRAM) even at low power supply voltages. For example, as the demand for devices requiring fast data processing and extended battery life grows, research into SRAMs with high-speed operation and low leakage current has occurred.

At least one example embodiment of the present disclosure provides a memory cell array of a static random access memory (SRAM), wherein the memory cell array is capable of high-speed operation with reduced leakage current and reduced area.

At least one example embodiment of the present disclosure provides an SRAM including the memory cell array.

According to example embodiments of the present disclosure, there is provided a memory cell array of an SRAM including: a top memory cell array including a plurality of top memory cells; and a bottom memory cell array including a plurality of bottom memory cells, wherein the plurality of top memory cells include: a first top memory cell connected between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, wherein the plurality of bottom memory cells include: a first bottom memory cell configured to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when a write operation and a read operation are not performed on the first top memory cell and the first bottom memory cell, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are electrically connected to the middle node.

According to example embodiments of the present disclosure, there is provided an SRAM including: a memory cell array including a top memory cell array and a bottom memory cell array, the top memory cell array including a plurality of top memory cells, the bottom memory cell array including a plurality of bottom memory cells; a row decoder connected to the memory cell array through a plurality of wordlines; and a column decoder connected to the memory cell array through a plurality of bitlines, wherein the plurality of top memory cells include: a first top memory cell connected between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, wherein the plurality of bottom memory cells include: a first bottom memory cell configured to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, and when a write operation and a read operation are not performed on the first top memory cell and the first bottom memory cell, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are electrically connected to the middle node.

According to example embodiments of the present disclosure, there is provided a memory cell array of an SRAM including: a top memory cell array including a plurality of top memory cells; and a bottom memory cell array including a plurality of bottom memory cells, wherein the plurality of top memory cells include: a first top memory cell connected between a power supply voltage and a middle node, and connected to a first top wordline, a first top bitline and a first top complementary bitline, the first top memory cell having a 6T structure with six transistors, the six transistors of the first top memory cell including two p-type metal oxide semiconductor (PMOS) pass gate transistors, wherein the plurality of bottom memory cells include: a first bottom memory cell configured to operate with the first top memory cell, connected between the middle node and a ground voltage, and connected to a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, the first bottom memory cell having a 6T structure with six transistors, the six transistors of the first bottom memory cell including two n-type metal oxide semiconductor (NMOS) pass gate transistors, when a write operation and a read operation are not performed on the first top memory cell and the first bottom memory cell, the first top bitline, the first top complementary bitline, the first bottom bitline and the first bottom complementary bitline are electrically connected to the middle node, when the write operation or the read operation is performed on the first top memory cell and the first bottom memory cell, the write operation or the read operation is performed on the first top memory cell and the first bottom memory cell, in a first time interval of the write operation or the read operation before the first top wordline and the first bottom wordline are enabled, a first top ground voltage of the first top memory cell decreases, and a first bottom power supply voltage of the first bottom memory cell increases, and in a second time interval of the write operation or the read operation after the first time interval, a voltage at the first top wordline corresponds to a logic low level, and a voltage at the first bottom wordline corresponds to a logic high level.

The memory cell array and the SRAM according to example embodiments of the present disclosure may be implemented with the fully-symmetric voltage-stacked (FSVS) structure. For example, the top memory cells and the bottom memory cells may be implemented with the voltage-stacked structure, and thus the leakage current may be reduced. In addition, a pair of top/bottom memory cells may be simultaneously accessed, the fully-symmetric operation may be performed on a pair of top/bottom memory cells, and thus the memory cell array and the SRAM may have relatively high operating speed. Further, all of the top memory cells and the bottom memory cells may be implemented to have the 6T structure, and thus the memory cell array and the SRAM may be industrially compatible, may have high process versatility and may have reduced area.

Various example embodiments of the present disclosure will be described more fully with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Like reference numerals may refer to like elements throughout this application.

is a block diagram illustrating a memory cell array of a static random access memory (SRAM) according to example embodiments.

Referring to, a memory cell arrayof an SRAM includes a top (or upper) memory cell arrayand a bottom (or lower) memory cell array.

The top memory cell arrayincludes a plurality of top (or upper) memory cells TMC, TMC, . . . , TMCp, where p is a natural number (or positive integer) greater than or equal to two. The top memory cell arraymay be a part of the memory cell array, and may be a sub-memory cell array or sub-array. The top memory cell arraymay be referred to as a top array, a first sub-memory cell array, a first sub-array, or the like.

The bottom memory cell arrayincludes a plurality of bottom (or lower) memory cells BMC, BMC, . . . , BMCp. Like the top memory cell array, the bottom memory cell arraymay be a part of the memory cell array, and may be a sub-memory cell array or a sub-array. The bottom memory cell arraymay be referred to as a bottom array, a second sub-memory cell array, a second sub-array, or the like.

One of the plurality of top memory cells TMCto TMCp and one of the plurality of bottom memory cells BMCto BMCp may operate as a pair. In addition, one of the plurality of top memory cells TMCto TMCp and one of the plurality of bottom memory cells BMCto BMCp may be connected to each other through one of a plurality of middle (or intermediate) nodes NM, NM, . . . , NMp.

For example, a first top memory cell TMCmay be connected to a first bottom memory cell BMCthrough a first middle node NM, and the first top memory cell TMCand the first bottom memory cell BMCmay operate as a pair. A second top memory cell TMCmay be connected to a second bottom memory cell BMCthrough a second middle node NM, and the second top memory cell TMCand the second bottom memory cell BMCmay operate as a pair. A p-th top memory cell TMCp may be connected to a p-th bottom memory cell BMCp through a p-th middle node NMp, and the p-th top memory cell TMCp and the p-th bottom memory cell BMCp may operate as a pair. Thus, the number of the plurality of top memory cells TMCto TMCp and the number of the plurality of bottom memory cells BMCto BMCp may be substantially equal to each other.

In some example embodiments, as will be described with reference to, one of the plurality of top memory cells TMCto TMCp and one of the plurality of bottom memory cells BMCto BMCp may be implemented with a voltage-stacked structure in which one of the plurality of top memory cells TMCto TMCp and one of the plurality of bottom memory cells BMCto BMCp are connected in series between a power supply voltage and a ground voltage. In this example, a middle voltage between the power supply voltage and the ground voltage may be formed at each of the plurality of middle nodes NMto NMp, and thus a leakage current may be reduced.

In some example embodiments, as will be described with reference to, each of the plurality of top memory cells TMCto TMCp and each of the plurality of bottom memory cells BMCto BMCp may have a 6T structure including six transistors. Each memory cell in a general SRAM may have the 6T structure, and thus the memory cell arrayaccording to example embodiments may be implemented with an industry-compatible structure.

In some example embodiments, as will be described with reference to, a structure of each of the plurality of top memory cells TMCto TMCp and a structure of each of the plurality of bottom memory cells BMCto BMCp may be very similar to each other, but they are not completely identical to each other. For example, some elements in each of the plurality of top memory cells TMCto TMCp and some elements in each of the plurality of bottom memory cells BMCto BMCp may be different from each other. For example, a configuration of pass gate transistors in each of the plurality of top memory cells TMCto TMCp and a configuration of pass gate transistors in each of the plurality of bottom memory cells BMCto BMCp may be different from each other. For example, a pass gate transistor in the first top memory cell TMCmay be different than a pass gate transistor in the first bottom memory cell BMC.

In some example embodiments, as will be described with reference to, a write operation or a read operation may be performed substantially simultaneously (or concurrently) and fully-symmetrically on one of the plurality of top memory cells TMCto TMCp and one of the plurality of bottom memory cells BMCto BMCp which operate as a pair. Thus, a pair of top and bottom memory cells may be accessed at one time, and the memory cell arrayand the SRAM including the memory cell arraymay have relatively high operating speed.

As described above, the memory cell arrayof the SRAM according to example embodiments may be implemented with the voltage-stacked structure, and may perform the fully-symmetric operation. Therefore, the memory cell arrayof the SRAM according to example embodiments may be referred to as a fully-symmetric voltage-stacked (FSVS) structure.

In some example embodiments, as will be described with reference to, while the write operation or the read operation is performed on one of the plurality of top memory cells TMCto TMCp and one of the plurality of bottom memory cells BMCto BMCp which operate as a pair, the minimum operating voltage may be reduced by the assist effect.

In some example embodiments, as will be described with reference to, the plurality of top memory cells TMCto TMCp and the plurality of bottom memory cells BMCto BMCp may be arranged in a two-dimensional (2D) matrix formation, and a configuration for an electrical connection with one middle node may be shared by two or more top memory cells and/or two or more bottom memory cells. For example, the first and second top memory cells TMCand TMCmay share the same middle node with the first and second bottom memory cells BMCand BMC.

As described above, the memory cell arrayof the SRAM according to example embodiments may be implemented with the FSVS structure. For example, the top memory cells TMCto TMCp and the bottom memory cells BMCto BMCp may be implemented with the voltage-stacked structure, and thus the leakage current may be reduced. In addition, a pair of top/bottom memory cells (e.g., the memory cells TMCand BMC) may be simultaneously accessed, the fully-symmetric operation may be performed on a pair of top/bottom memory cells, and thus the memory cell arrayand the SRAM may have relatively high operating speed. Further, all of the top memory cells TMCto TMCp and the bottom memory cells BMCto BMCp may be implemented to have the 6T structure, and thus the memory cell arrayand the SRAM may be industrially compatible, may have high process versatility and may have reduced area.

is a block diagram illustrating an example of a pair of a top memory cell and a bottom memory cell included in a memory cell array of.

Referring to, a top memory cell TMC may be connected between a power supply voltage Vand a middle node NM, and may be connected to a top wordline WL, a top bitline BLand a top complementary (or inverted) bitline BLB. A bottom memory cell BMC operating as a pair with the top memory cell TMC may be connected between the middle node NM and a ground voltage V, and may be connected to a bottom wordline WL, a bottom bitline BLand a bottom complementary (or inverted) bitline BLB. For example, a middle voltage Vmay be formed at the middle node NM, e.g., V=0.5*V.

The top memory cell TMC may be one of the plurality of top memory cells TMCto TMCp in. The bottom memory cell BMC may be one of the plurality of bottom memory cells BMCto BMCp in. The middle node NM may be one of the plurality of middle nodes NMto NMp in.

For example, when the top memory cell TMC, the middle node NM and the bottom memory cell BMC are the first top memory cell TMC, the first middle node NMand the first bottom memory cell BMCin, respectively, the top wordline WL, the top bitline BLand the top complementary bitline BLBmay be a first top wordline, a first top bitline and a first top complementary bitline, respectively, and the bottom wordline WL, the bottom bitline BLand the bottom complementary bitline BLBmay be a first bottom wordline, a first bottom bitline and a first bottom complementary bitline, respectively. When the top memory cell TMC, the middle node NM and the bottom memory cell BMC are the second top memory cell TMC, the second middle node NMand the second bottom memory cell BMCin, respectively, the top wordline WL, the top bitline BLand the top complementary bitline BLBmay be a second top wordline, a second top bitline and a second top complementary bitline, respectively, and the bottom wordline WL, the bottom bitline BLand the bottom complementary bitline BLBmay be a second bottom wordline, a second bottom bitline and a second bottom complementary bitline, respectively. When the top memory cell TMC, the middle node NM and the bottom memory cell BMC are the p-th top memory cell TMCp, the p-th middle node NMp and the p-th bottom memory cell BMCp in, respectively, the top wordline WL, the top bitline BLand the top complementary bitline BLBmay be a p-th top wordline, a p-th top bitline and a p-th top complementary bitline, respectively, and the bottom wordline WL, the bottom bitline BLand the bottom complementary bitline BLBmay be a p-th bottom wordline, a p-th bottom bitline and a p-th bottom complementary bitline, respectively.

The voltage-stacked structure may be a circuit implementation technique in which circuits are stacked in series to form a middle voltage, thereby reducing power consumption of a low dropout regulator (LDO) using a conventional voltage drop scheme. In other words, the voltage-stacked structure is a circuit design where circuits are arranged in series to create an intermediate voltage. This structure can help reduce the power consumption of an LDO, which uses a less efficient voltage drop scheme. Since the SRAM has a symmetrical structure, the middle voltage may be maintained at a half of the power supply voltage when the voltage-stacked structure is applied to the SRAM, and thus the SRAM may be suitable for having the voltage-stacked structure. In the memory cell arrayimplemented with the FSVS structure according to example embodiments, each top memory cell TMC included in the top memory cell arrayand each bottom memory cell BMC included in the bottom memory cell arraymay be stacked in series from the power supply voltage Vto the ground voltage V. Accordingly, V=0.5*Vmay be formed stably, and the leakage current may be reduced.

is a circuit diagram illustrating an example of a top memory cell and a bottom memory cell in.

Referring to, a top memory cellmay be connected between the power supply voltage Vand the middle node NM, and may be connected to the top wordline WL, the top bitline BLand the top complementary bitline BLB. The top memory cellmay include top p-type metal oxide semiconductor (PMOS) transistors TPU, TPU, TPGand TPG, and top n-type metal oxide semiconductor (NMOS) transistors TPDand TPD.

The top PMOS transistor TPUand the top NMOS transistor TPDmay be connected in series between a top power supply voltage CVand a top ground voltage CVSS, and each of the top PMOS transistor TPUand the top NMOS transistor TPDmay include a gate electrode connected to a node TQB. The top PMOS transistor TPUand the top NMOS transistor TPDmay be connected in series between the top power supply voltage CVand the top ground voltage CVSS, and each of the top PMOS transistor TPUand the top NMOS transistor TPDmay include a gate electrode connected to a node TQ. The top power supply voltage CVmay be substantially equal to the power supply voltage V, and the top ground voltage CVSSmay be substantially equal to or different from a voltage at the middle node NM, e.g., the middle voltage V, depending on an operating state of the top memory cell. The top PMOS transistor TPGmay be connected between the node TQ and the top bitline BL, and may include a gate electrode connected to the top wordline WL. The top PMOS transistor TPGmay be connected between the node TQB and the top complementary bitline BLB, and may include a gate electrode connected to the top wordline WL.

A bottom memory cellmay be connected between the middle node NM and the ground voltage V, and may be connected to the bottom wordline WL, the bottom bitline BLand the bottom complementary bitline BLB. The bottom memory cellmay include bottom PMOS transistors BPUand BPU, and bottom NMOS transistors BPD, BPD, BPGand BPG.

The bottom PMOS transistor BPUand the bottom NMOS transistor BPDmay be connected in series between a bottom power supply voltage CVDDand a bottom ground voltage CV, and each of the bottom PMOS transistor BPUand the bottom NMOS transistor BPDmay include a gate electrode connected to a node BQB. The bottom PMOS transistor BPUand the bottom NMOS transistor BPDmay be connected in series between the bottom power supply voltage CVDDand the bottom ground voltage CV, and each of the bottom PMOS transistor BPUand the bottom NMOS transistor BPDmay include a gate electrode connected to a node BQ. The bottom power supply voltage CVDDmay be substantially equal to or different from the voltage at the middle node NM, e.g., the middle voltage V, depending on an operating state of the bottom memory cell, and the bottom ground voltage CVmay be substantially equal to the ground voltage V. The bottom NMOS transistor BPGmay be connected between the node BQ and the bottom bitline BL, and may include a gate electrode connected to the bottom wordline WL. The bottom NMOS transistor BPGmay be connected between the node BQB and the bottom complementary bitline BLB, and may include a gate electrode connected to the bottom wordline WL.

Among the transistors included in the top memory celland the bottom memory cell, the top PMOS transistors TPUand TPUand the bottom PMOS transistors BPUand BPUmay be referred to as pull-up transistors, the top NMOS transistors TPDand TPDand the bottom NMOS transistors BPDand BPDmay be referred to as pull-down transistors, and the top PMOS transistors TPGand TPGand the bottom NMOS transistors BPGand BPGmay be referred to as pass-gate transistors.

As described above, both the top memory celland the bottom memory cellmay have the 6T structure including six transistors. For example, the bottom memory cellmay include two PMOS transistors and four NMOS transistors, and two pass gate transistors included in the bottom memory cellmay be implemented as NMOS transistors. For example, the top memory cellmay include four PMOS transistors and two NMOS transistors, and two pass gate transistors included in the top memory cellmay be implemented as PMOS transistors. In other words, the bottom memory cellmay include two NMOS pass-gate transistors and the top memory cellmay include two PMOS pass-gate transistors. In this example, a high density cell (HDC), which is a memory cell of a general SRAM, may be used as the bottom memory cell, and a custom cell in which pass gate transistors of the HDC are changed from NMOS transistors to PMOS transistors may be used as the top memory cell.

In some example embodiments, top switches TSW, TSWand TSWfor electrically connecting/disconnecting the top memory cellto/from the middle node NM may be provided, and bottom switches BSW, BSWand BSWfor electrically connecting/disconnecting the bottom memory cellto/from the middle node NM may be provided. For example, the top switches TSWto TSWand the bottom switches BSWto BSWmay not be included in the top memory celland the bottom memory celland/or may not be included in the memory cell array. In, the top switches TSWto TSWand the bottom switches BSWto BSWare illustrated to describe an electrical connection/disconnection between the memory cellsandand the middle node NM depending on the operating states of the memory cellsand. For example, the top switches TSWto TSWand the bottom switches BSWto BSWmay be included in a peripheral circuit that drives the memory cellsandand the memory cell array. For example, the top switches TSWto TSWand the bottom switches BSWto BSWmay be included in a row decoder (e.g., a row decoderin) and/or a column decoder (e.g., a column decoderin).

are diagrams for describing an operation of a top memory cell and a bottom memory cell in.

Referring to, an example where the write operation and the read operation are not performed on the top memory celland the bottom memory cellis illustrated. In other words,illustrates an operation in a standby state or a hold state. For example, as illustrated in, all of the top switches TSWto TSWand the bottom switches BSWto BSWmay be turned on and may be closed.

When the write operation and the read operation are not performed on the top memory celland the bottom memory cell, the top ground voltage CVSSand the bottom power supply voltage CVDDmay be electrically connected to the middle node NM and the middle voltage V, and leakage current may be recycled as illustrated by arrows “I.” For example, both the top ground voltage CVSSand the bottom power supply voltage CVDDmay be substantially equal to the middle voltage V.

In addition, when the write operation and the read operation are not performed on the top memory celland the bottom memory cell, all of the top bitline BL, the top complementary bitline BLB, the bottom bitline BLand the bottom complementary bitline BLBmay be electrically connected to the middle node NM and the middle voltage V, and leakage current may be recycled as illustrated by arrows “I.” As compared with a conventional scheme, all bitlines and complementary bitlines may be additionally connected to the middle node NM in the example of. Accordingly, the leakage current may be completely recycled, and the leakage current may be further reduced by forming V=0.5*Vstably.

Referring to, an example where the write operation or the read operation is performed on the top memory celland the bottom memory cellis illustrated. For example, as illustrated in, all of the top switches TSWto TSWand the bottom switches BSWto BSWmay be turned off and may be opened.

When the write operation or the read operation is performed on the top memory celland the bottom memory cell, the top ground voltage CVSSand the bottom power supply voltage CVDDmay be electrically disconnected (or separated) from the middle node NM and the middle voltage V, and both the top ground voltage CVSSand the bottom power supply voltage CVDDmay become different from the middle voltage V. For example, the top ground voltage CVSSmay become lower than the middle voltage V, and the bottom power supply voltage CVDDmay become higher than the middle voltage V. In other words, voltages of the top memory celland the bottom memory cellnear the middle node NM may be different from each other. Since the SRAM is vulnerable to variations in transistors due to its cell structure, the voltages should be sufficiently high during operation, and thus it may be necessary to decrease the level of the top ground voltage CVSSand to increase the level of the bottom power supply voltage CVDD. For example, the above-described voltage control operation may be required before the wordline is enabled or activated to perform the write operation or the read operation, which will be described with reference to.

In addition, when the write operation or the read operation is performed on the top memory celland the bottom memory cell, all of the top bitline BL, the top complementary bitline BLB, the bottom bitline BLand the bottom complementary bitline BLBmay be electrically disconnected from the middle node NM and the middle voltage V. In this example, the top memory cellmay be enabled through the top wordline WL, the top bitline BL, and the top complementary bitline BLB, the bottom memory cellmay be enabled through the bottom wordline WL, the bottom bitline BLand the bottom complementary bitline BLB, and current may be generated as illustrated by arrows to perform the write operation or the read operation.

In some example embodiments, the pass gate transistors included in the top memory cellmay be implemented as PMOS transistors TPGand TPG, and the pass gate transistors included in the bottom memory cellmay be implemented as NMOS transistors BPGand BPG. Thus, the top memory celland the bottom memory cellmay be substantially simultaneously enabled, and the write operation or the read operation may be substantially simultaneously performed on the top memory celland the bottom memory cell. For example, the top memory cellmay be enabled when a voltage level of the top wordline WLbecomes a logic low level “0,” and the bottom memory cellmay be enabled when a voltage level of the bottom wordline WLbecomes a logic high level “1.” For example, data “0” and “1” in the top memory cellmay correspond to 0.5*Vand V, respectively, and data “0” and “1” in the bottom memory cellmay correspond to V(e.g., about 0V) and 0.5*V, respectively.

are plan views of an example layout of a top memory cell and a bottom memory cell in.

Referring to,illustrates a layout of the top memory cellformed on a semiconductor substrate, andillustrates a layout of the bottom memory cellformed on a semiconductor substrate. In, “N-well” represents an n-type well region, “Contact” represents a contact pattern, “M” and “M” represent metal patterns formed on different layers, “Via” and “Via” represent vias for connecting different layers, and “G-poly” represents a gate polysilicon pattern. In addition, “PU”, “PD” and “PG” represent a pull-up transistor, a pull-down transistor and a pass gate transistor, respectively.

As illustrated in, the layout of the bottom memory cellmay be substantially the same as that of the HDC which is currently used. For example, in the bottom memory cell, the pull-up transistors PU may be implemented as PMOS transistors, and the pull-down transistors PD and the pass gate transistors PG may be implemented as NMOS transistors.

As illustrated in, the layout of the top memory cellmay be partially changed from the layout of the bottom memory cellof. For example, in the top memory cell, the pull-up transistors PU and the pass gate transistors PG may be implemented as PMOS transistors, and the pull-down transistors PD may be implemented as NMOS transistors. In other words, the pass gate transistors PG may be implemented as PMOS transistors unlike that of the HDC illustrated in. Furthermore, the custom cell illustrated inmay be formed by changing some elements of the HDC illustrated in. For example, the layout of the top memory cellofmay be implemented by swapping positions of n-type and p-type well regions in the layout of the bottom memory cellof, by swapping positions of CVand CVlines in the layout of the bottom memory cellof, and by swapping positions of pull-up and pull-down transistors PU and PD in the layout of the bottom memory cellof.