Semiconductor device, semiconductor package, and memory system

This application claims benefit of priority to Korean Patent Application No. 10-2021-0157518 filed on Nov. 16, 2021 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

The present inventive concepts relate to a semiconductor device, a semiconductor package, and/or a memory system.

A semiconductor device may include pads connected to another external semiconductor device, and the pads are included in the semiconductor device and may be connected to an input/output (I/O) circuit including at least one of a transmitter and a receiver. Such a semiconductor device may transmit and receive signals to and from other semiconductor devices through the pads. In general, the pads of different semiconductor devices are physically connected to each other to send and receive signals, and recently, a method of forming a coil in pads and letting semiconductor devices exchange signals using electromagnetic induction due to current flowing through the coil has been actively researched.

Some example embodiments of the present inventive concepts provide a semiconductor device, a semiconductor package, and/or a memory system, in which input/output (I/O) circuits of different semiconductor devices are connected to each other using a via structure passing through the center of a coil pattern for exchanging signals, and a different signal is exchanged with the coil pattern through the via structure, thereby improving the degree of integration and performance.

According to an example embodiment of the present inventive concepts, a semiconductor device includes an element region including a semiconductor substrate and a plurality of elements formed on the semiconductor substrate and a wiring region disposed on the element region and including an interlayer insulating layer, a plurality of wiring patterns in the interlayer insulating layer, and a via structure extending in a first direction, perpendicular to an upper surface of the semiconductor substrate, in the interlayer insulating layer, wherein the plurality of elements includes a first input/output (I/O) circuit transmitting and receiving a first signal and a second I/O circuit transmitting and receiving a second signal, different from the first signal, the plurality of wiring patterns is a coil pattern includes an inductor circuit, the coil pattern is connected to the first I/O circuit, and the via structure passes through a center of the coil pattern and is connected to the second I/O circuit.

According to an example embodiment of the present inventive concepts, a semiconductor package includes a package substrate and a first semiconductor device and a second semiconductor device stacked in a first direction, perpendicular to an upper surface of the package substrate, wherein each of the first semiconductor device and the second semiconductor device includes a semiconductor substrate, a plurality of via structures passing through the semiconductor substrate, a coil pattern surrounding at least one via structure of the plurality of via structures in a second direction, parallel to an upper surface of the semiconductor substrate, and an input/output (I/O) circuit connected to at least one of the plurality of via structures and the coil pattern, the at least one via structure provides a transmission path of a first signal, and the coil pattern provides a transmission path of a second signal, different from the first signal.

According to an example embodiment of the present inventive concepts, a memory system includes a printed circuit board (PCB), a host device on the PCB, and a memory package on the PCB, the memory package including a plurality of memory devices stacked on each other, and connected to the host device, wherein the plurality of memory devices includes a plurality of through-silicon vias (TSVs) and a plurality of coil patterns surrounding at least one of the plurality of TSVs, and the plurality of memory devices exchange signals with the host device through the plurality of TSVs and the plurality of coil patterns.

Hereinafter, example embodiments of the present inventive concepts will be described with reference to the accompanying drawings.

is a schematic block diagram illustrating a system including a semiconductor device according to an example embodiment of the present inventive concepts.

Referring to, a systemaccording to an example embodiment of the present inventive concepts may include a first semiconductor deviceand a second semiconductor device. The first semiconductor deviceand the second semiconductor device may be connected to each other for communication with each other. The first semiconductor deviceand the second semiconductor devicemay be communicatively coupled to each other. The first semiconductor devicemay include an internal circuit, an input/output (I/O) circuit, a plurality of coil patternsand, and a plurality of padsand. The second semiconductor devicemay include an internal circuit, an I/O circuit, a plurality of coil patternsand, and a plurality of padsand.

In an example embodiment, the internal circuitof the first semiconductor deviceand the internal circuitof the second semiconductor devicemay have different structures and may perform different functions. For example, when the first semiconductor deviceis an application processor, the internal circuitmay include a CPU, GPU, DSP, NPU, a memory interface, a display interface, a power circuit, and the like. When the second semiconductor deviceis a memory device connected to an application processor, the internal circuitmay include a memory cell array in which memory cells are disposed and peripheral circuits controlling the memory cell array.

The first semiconductor deviceand the second semiconductor devicemay transmit and receive signals through a plurality of coil patterns,,, and. For example, the plurality of coil patterns,,, andmay be inductor circuits provided by internal wiring patterns of the first semiconductor deviceand the second semiconductor device. The first semiconductor deviceand the second semiconductor devicemay transmit and receive signals using electromagnetic induction between a pair of coil patterns,,, andcoupled to each other.

Also, the first semiconductor deviceand the second semiconductor devicemay exchange signals with each other through the plurality of pads,,, and. For example, the first semiconductor deviceand the second semiconductor devicemay be stacked on each other, and the plurality of padsandincluded in the first semiconductor devicemay be connected to the plurality of padsandincluded in the second semiconductor devicevia structures. The first semiconductor deviceand the second semiconductor devicemay exchange signals with each other through the via structures.

In an example embodiment illustrated in, some pads,among the plurality of pads,,, andmay be disposed in the center of the coil patterns,,and. Via structures connecting the padsandto each other may pass through the center of the coil patterns,,, and.

The padsandmay transmit signals like other padsand. In an example embodiment, when the first semiconductor deviceis an application processor and the second semiconductor deviceis a memory device, the first semiconductor devicemay transmit a power voltage required for an operation of the second semiconductor device, together with signals such as a data signal, a system clock signal, and a data strobe signal, to the second semiconductor device. For example, the first semiconductor deviceand the second semiconductor devicemay exchange data signals through the coil patterns,,, and. Meanwhile, the first semiconductor devicemay supply a power voltage to the second semiconductor devicethrough some padsanddisposed in the centers of the coil patterns,,, and.

However, this is only an example embodiment, and the first semiconductor deviceand the second semiconductor devicemay exchange signals other than the power voltage through some padsanddisposed in the center of the coil patterns,,and. In this manner, in an example embodiment of the present inventive concepts, the padsandmay be disposed in the center of the coil patterns,,and, and the padsandare connected to the via structure and used as a signal transmission path. Accordingly, a signal transmission path between the semiconductor devicesandmay be effectively secured, and the degree of integration of each of the semiconductor devicesandmay be improved.

are diagrams illustrating an operation of a semiconductor device according to an example embodiment of the present inventive concepts.

Referring to, a first semiconductor deviceand a second semiconductor deviceaccording to an example embodiment of the present inventive concepts may exchange signals with each other using electromagnetic induction due to current flowing through the coil patternsand. In the example embodiments illustrated in, the first semiconductor devicetransmits a signal and the second semiconductor devicereceives the signal, but conversely, the second semiconductor devicemay transmit a signal, and the first semiconductor devicemay receive the signal.

Referring to, a transmitting circuitmay be connected to the coil patternin the first semiconductor device, and a receiving circuitmay be connected to the coil patternin the second semiconductor device. Referring to, the transmitting circuitmay apply a first current Iflowing in a first direction to the coil pattern. When the first current Iflows through the coil pattern, electromagnetic induction may occur in the coil patternsandcoupled to each other as illustrated in, and a voltage may be induced to both ends of the coil patternof the second semiconductor device. Also, the second current Imay flow through the coil patternin the first direction.

Next, referring to, the transmitting circuitmay apply a first current Iflowing in a second direction opposite to the first direction to the coil pattern. For example, in the example embodiments illustrated in, the first direction may be a counterclockwise direction, and the second direction may be a clockwise direction. When the first current Iflows through the coil patternin the second direction, electromagnetic induction may occur in the coil patternsandcoupled to each other and a voltage may be induced to both ends of the coil patternof the second semiconductor device. Also, a second current Iflowing in the second direction may be induced through the coil pattern.

The receiving circuitof the second semiconductor devicemay determine data included in the signal transmitted by the first semiconductor devicebased on the voltage induced in the coil pattern. For example, when data ‘0’ is to be transmitted, a voltage may be applied to both ends of the coil pattern so that the first current Imay flow in the first direction in the coil pattern. Conversely, when data ‘1’ is to be transmitted, a voltage may be applied to both ends of the coil patternso that the first current Imay flow in the second direction in the coil pattern.

The voltage induced in the coil patternof the second semiconductor devicemay vary according to a direction of the first current Iflowing in the coil patternof the first semiconductor device. Accordingly, the receiving circuitof the second semiconductor devicemay determine data included in the signal transmitted by the first semiconductor devicebased on the voltage induced in the coil pattern.

are diagrams schematically illustrating a semiconductor device according to an example embodiment of the present inventive concepts.

First, referring to, a semiconductor deviceaccording to an example embodiment of the present inventive concepts may include an internal circuit, a transmitter Tx, a receiver Rx, and a plurality of coil patternsand. The plurality of coil patternsandmay include a first coil patternconnected to an output terminal of the transmitter Tx and a second coil patternconnected to an input terminal of the receiver Rx.

The internal circuitmay include a plurality of circuits for implementing a function of the semiconductor device. For example, when the semiconductor deviceis a memory device, the internal circuitmay include a power supply circuit, a decoder circuit, a page buffer, a memory cell array, and the like. When the semiconductor deviceis an application processor, the internal circuitmay include a core, a GPU, a DSP, a memory controller, a power supply circuit, and the like.

The internal circuitmay output a signal to an external semiconductor device through the transmitter Tx and the first coil pattern. The internal circuitmay output a desired signal by controlling a direction of a current flowing through the first coil patternthrough the transmitter Tx. An induced voltage may be generated in a coil pattern included in another semiconductor device adjacent to the semiconductor deviceaccording to a current flowing through the first coil pattern. In an example embodiment, an internal circuit of the another semiconductor device may receive a signal output by the semiconductor deviceby comparing the induced voltage with a predetermined reference voltage.

Also, the internal circuitmay receive a signal from another external semiconductor device through the receiver Rx and the second coil pattern. An induced voltage may be generated in the second coil patterndue to a current flowing through a coil pattern of the other external semiconductor device. The receiver Rx may compare the induced voltage generated in the second coil patternwith a predetermined reference voltage, and the internal circuitmay receive a signal output from the another semiconductor device.

In the example embodiment illustrated in, the first coil patternmay be connected to the transmitter Tx and the second coil patternmay be connected to the receiver Rx. Meanwhile, in the semiconductor deviceaccording to the example embodiment illustrated in, a single coil patternmay be connected to an output terminal of a transmitter Tx and an input terminal of a receiver Rx. Therefore, in the example embodiment illustrated in, the semiconductor devicemay include a first switch SWand a second switch SWso that the coil patternis not simultaneously connected to the transmitter Tx and the receiver Rx.

The first switch SWmay be a transmission switch connected between the output terminal of the transmitter Tx and the coil pattern. Meanwhile, the second switch SWmay be a reception switch connected between the input terminal of the receiver Rx and the coil pattern. Each of the first switch SWand the second switch SWis turned on and turned off by an internal circuit, and the first switch SWand the second switch SWmay not be simultaneously turned on.

In the case of outputting a signal to another semiconductor device, the internal circuitmay turn on the first switch SWand turn off the second switch SWto connect the coil patternto the output terminal of the transmitter Tx. Meanwhile, in the case of receiving a signal from another semiconductor device, the internal circuitmay turn off the first switch SWand turn on the second switch SWto connect the coil pattern () to the input terminal of the receiver Rx.

are diagrams schematically illustrating a semiconductor package according to an example embodiment of the present inventive concepts.

Referring to, a semiconductor packageaccording to an example embodiment may include a first semiconductor deviceand a second semiconductor device, and the first semiconductor deviceand the second semiconductor devicemay be stacked each other. The first semiconductor deviceand the second semiconductor devicemay include the I/O circuits,,, and, coil patternsandconnected to the first I/O circuitsand, and a via structureconnected to the second I/O circuitsand.

The I/O circuits,,, andof the first semiconductor deviceand the second semiconductor devicemay include a transmitter, a receiver, and a sampling circuit. Meanwhile, the coil patternsandmay be connected to an output terminal of a transmitter and an input terminal of a receiver included in the first I/O circuitsand, and the coil patternof the first semiconductor devicemay be aligned with the coil patternof the semiconductor device.

Accordingly, an induced voltage may be generated in the coil patternof the second semiconductor devicedue to the current flowing in the coil patternof the first semiconductor device, and conversely, an induced voltage may be generated in the coil patternof the first semiconductor devicedue to the current flowing in the coil patternof the second semiconductor device. In the example embodiment illustrated in, each of the coil patternsandis simply illustrated. However, the shape and number of turns of the coil patternsandmay be variously modified, unlike those illustrated in.

Referring to, the semiconductor packagemay include the via structurepassing through the center of the coil patternsand. The via structuremay extend in a direction in which the first semiconductor deviceand the second semiconductor deviceare stacked. Also, the via structuremay provide a signal transmission path between the first semiconductor deviceand the second semiconductor device. In other words, the first semiconductor deviceand the second semiconductor devicemay transmit and receive signals through the via structure. In an example embodiment, the via structuremay be connected to the second I/O circuitsand, and a transmitter and a receiver included in the second I/O circuitsandmay output or receive a signal through the via structure.

For example, the via structuremay be a through-silicon via (TSV) passing through the semiconductor substrate included in the first semiconductor device. In addition, the via structuremay be formed of a material having a low resistivity so that a signal may be efficiently transmitted. As illustrated in, the via structuremay be disposed to pass through the center of the coil patternsandand the first semiconductor deviceand the second semiconductor devicemay be designed to exchange signals through the via structure, so that the degree of integration of each of the first semiconductor deviceand the second semiconductor devicemay be improved.

In an example embodiment, a signal transmitted through the coil patternsandmay be different from a signal transmitted through the via structure. For example, the first semiconductor deviceand the second semiconductor devicemay transmit and receive a data signal, a data strobe signal, and the like, and may exchange a power signal through the via structure. However, this is only an example embodiment, and the signal transmitted through the coil patternsandand the signal transmitted through the via structuremay be variously modified.

Next, referring to, a semiconductor packageA according to an example embodiment of the present inventive concepts may include a first semiconductor deviceand a second semiconductor device, and the first semiconductor deviceand the second semiconductor devicemay be stacked on each other. Each of the first semiconductor deviceand the second semiconductor devicemay include I/O circuits,,, and, coil patternsandconnected to the first I/O circuitsand, and a plurality of via structuresto() connected to the second I/O circuitsand, and the like. Signal transmission/reception between the first semiconductor deviceand the second semiconductor deviceby the operation of the first I/O circuitsandand the coil patternsandmay be understood based on the descriptions given above with reference to.

Referring to, the semiconductor packageA may include a plurality of via structurespassing through the centers of the coil patternsand. The plurality of via structuresmay be connected to the second I/O circuitsand, and the second I/O circuitsandmay include a plurality of transmitters and a plurality of receivers connected to a plurality of via structures. Each of the plurality of via structuresmay be arranged in one direction or may be arranged in a matrix form. The plurality of via structuresmay have the same cross-sectional area and may be formed of a material having high conductivity.

In the example embodiment illustrated in, the plurality of via structuresadjacent to each other and surrounded by the coil patternsandmay provide a transmission path for the same type of signal. For example, the plurality of via structuresmay provide transmission paths for a plurality of data signals. Also, as described above, signals transmitted and received between the first semiconductor deviceand the second semiconductor devicethrough the coil patternsandmay be different from signals transmitted and received through the plurality of via structures.

Meanwhile, referring to, a semiconductor packageB according to an example embodiment may include a first semiconductor deviceand a second semiconductor devicestacked on each other, and each of the first semiconductor deviceand the second semiconductor devicemay include I/O circuits,,, and, coil patternsandconnected to the first I/O circuitsand, a plurality of via structuresto(), and the like. Signal transmission and reception by the operation of the first I/O circuitsandand the coil patternsandmay be the same as described above with reference to.

Referring to, the semiconductor packageA may include the plurality of via structurespassing through the centers of the coil patternsand. The plurality of via structuresmay have the same cross-sectional area.

In an example embodiment illustrated in, at least one via structureamong the plurality of via structuresmay be formed of a material different from that of the other via structuresto. For example, the at least one via structuremay be formed of a first material having ferromagnetic characteristics, and the other via structurestomay be formed of a second material having resistivity lower than that of the first material. Accordingly, the other via structurestomay have conductivity higher than that of the at least one via structure.

The first semiconductor deviceand the second semiconductor devicemay exchange signals with each other through the coil patternsandand the via structuresto. At least one via structureformed of a ferromagnetic material may not be connected to the second I/O circuitsand, unlike the via structuresto. Since at least one via structureformed of a ferromagnetic material is disposed to pass through the center of the coil patternsand, a coupling coefficient may be improved without increasing a cross-sectional area of the coil patternsand. Accordingly, signal transmission efficiency through the coil patternsandmay be improved without degrading the degree of integration of the first semiconductor deviceand the second semiconductor device.

In the example embodiment illustrated in, at least one via structureformed of a ferromagnetic material may be disposed between the other via structuresto, and the same number of the remaining via structurestomay be distributed and disposed on both sides of the at least one via structure. However, this is only an example embodiment, and an arrangement order and shape of the via structureformed of the first material having ferromagnetic characteristics and the via structurestoformed of the second material having low resistivity may be variously modified. In addition, the number of via structureshaving ferromagnetic characteristics may also vary according to example embodiments.

Referring to, a semiconductor packageC according to an example embodiment may include a first semiconductor deviceand a second semiconductor devicestacked on each other. Each of the first semiconductor deviceand the second semiconductor devicemay include I/O circuits,,, andand coil patternsandconnected to the first I/O circuitsand, and signal transmission/reception between the first semiconductor deviceand the second semiconductor devicethrough the coil patternsandmay be the same as described above.

Referring to, the semiconductor packageC may include a plurality of via structuresto() passing through the centers of the coil patternsand. As described above with reference to, at least one via structureof the plurality of via structuresmay be formed of a first material having ferromagnetic characteristics, and the other via structurestomay be formed of a second material having excellent conductivity. The other via structurestoformed of the second material may be connected to the second I/O circuitsand.

In the example embodiment illustrated in, at least one via structureformed of the first material may have a relatively large cross-sectional area compared to the other via structuresto. Accordingly, a coupling coefficient of the coil patternsandmay be increased and signal transmission efficiency through the coil patternsandmay be further improved.

Meanwhile, in a semiconductor packageD according to an example embodiment illustrated in, a via structureformed of a ferromagnetic material, among a plurality of via structuresto(), may have a smaller cross-sectional area, compared with the other via structurestoformed of a material having high conductivity. Accordingly, via structurestoas many as possible may be disposed in a region formed inside the coil patternsandand utilized as a signal transmission path, and the degree of integration of each of the first semiconductor deviceand the second semiconductor devicemay be improved.

As described with reference to, the first semiconductor deviceand the second semiconductor devicetransmit signals through the coil patternsandas well as exchanging signals with each other through the via structures,,,, anddisposed to pass through the center of the coil patternsand. For example, through the via structures,,,, and, a power signal may be transmitted between the first semiconductor deviceand the second semiconductor deviceor a signal different from the power signal may be transmitted. This will be described in more detail with reference tohereinafter.