Method for forming memory patterns and wire patterns simultaneously

The present disclosure relates to a method for forming a semiconductor memory structure, and in particular, it relates to Dynamic Random Access Memory.

In order to increase DRAM density and improve its performance, existing technologies for fabricating DRAM devices continue to focus on scaling down the DRAM size.

The method of forming a semiconductor memory structure includes forming a conductive material over a dielectric structure, and forming a first patterned hard mask layer over the conductive material. The first patterned hard mask layer includes first strip patterns and a mesa pattern connected to the first strip patterns. The method also includes forming a second patterned hard mask layer over the first patterned hard mask layer. The second patterned hard mask layer includes second strip patterns overlapping the first strip patterns and first wire patterns overlapping the mesa pattern. The method also includes etching the first patterned hard mask layer using the second patterned hard mask layer. Remaining portions of the first strip patterns form pad patterns, and remaining portions of the mesa pattern form second wire patterns. The method also includes transferring the pad patterns and the second wire patterns into the conductive material.

The method of forming a semiconductor memory structure includes forming a first hard mask layer over a semiconductor substrate. The semiconductor substrate includes a memory cell array region and a periphery circuitry region. The method also includes forming first strip patterns over the first hard mask layer. The first strip patterns continuously extend in the memory cell array region and the periphery circuitry region. The method also includes forming a photoresist pattern over the first strip patterns to cover the periphery circuitry region while exposing the memory cell array region, etching the first hard mask layer using the photoresist pattern and the first strip patterns to form second strip patterns in the memory cell array region and a mesa pattern in the periphery circuitry region, and patterning the second strip patterns and the mesa pattern of the first hard mask layer to form pad patterns in the memory cell array region and wire patterns in the periphery circuitry region respectively.

Referring to, a semiconductor structureincluding a substrateand a dielectric structureover the substrateis provided. The substratemay be defined as various device regions, e.g., a memory cell array regionA, a peripheral circuitry regionB, and/or another applicable region. Left parts of theillustrate the memory cell array regionA which corresponds to Cross section A-A in the plan views. Right parts of theillustrate the peripheral circuitry regionB which corresponds to Cross section B-B in the plan views. The peripheral circuitry regionB is disposed adjacent to the memory cell array regionA. Memory cells (e.g., DRAMs) are formed in the memory cell array regionA and are operable as data storage. Peripheral circuitry devices are formed in the peripheral circuitry regionB and are operable to access and/or control (e.g., perform read/write/erase operation) the memory cells in the memory cell array regionA, in accordance with some embodiments.

In some embodiments, the substratemay be or includes a semiconductor substrate. The semiconductor substrate may be an elemental semiconductor substrate or a compound semiconductor substrate.

In the memory cell array regionA of the substrate, the memory cells may include gate structures (e.g., serving as word lines) embedded in the semiconductor substrate, and bit lines disposed over the semiconductor substrate. Word lines extend through active regions of the substrateand combine with the source/drain regions in the active regions to form embedded transistors. The bit lines may be electrically connected to some source/drain regions in the active regions. Contact plugsare disposed in the dielectric structureand are electrically connected to some other source/drain regions in the active regions. Conductive pads(or may be referred to as landing pads) are disposed over the dielectric structureand disposed correspondingly over the contact plugs. In addition, the dummy conductive padsD are disposed at the edge of the memory cell array regionA.

In the peripheral circuitry regionB of the substrate, the periphery circuitry devices may include planar transistors and/or multi-gate transistors, which may include gate structures formed over the semiconductor substrate. Contact plugsare disposed in the dielectric structure, and wiresare disclosed over the dielectric structure. The wiresare electrically connected to the gate structures and/or source/drain regions of the periphery circuitry devices through the contact plugs.

The conductive padsin the memory cell array regionA and the wiresin the peripheral circuitry regionB are a portion of an interconnect structure and may be the metallic patterns located at the same level (e.g., M1 layer). In some embodiments of the present disclosure, the conductive padsand the wireare formed at the same time, and formed by transferring pad patternsand wire patternsB into a conductive material using patterned hard mask layersA andB. The method of forming the conductive padsin the memory cell array regionA and the wiresin the peripheral circuitry regionB are described in detail below.

Referring to, a dielectric structureis formed over the substrate. The dielectric structuremay include one or more dielectric materials such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), a multilayer thereof, and/or a combination thereof. Openingsare formed in the dielectric structurein the memory cell array regionA by patterning processes (e.g., including photolithography processes and etching processes).

Referring to, one or more conductive material(s)is formed over the dielectric structureto overfill the openings. The portion of the conductive materialformed in the openingsmay serve as the contact plugshown in. The conductive materialmay include polysilicon, metal silicide (such as cobalt silicide (CoSi), nickel silicide (NiSi), titanium silicide (TiSi) or tungsten silicide (WSi)), metal nitride (such as titanium nitride (TiN) or tantalum nitride (TaN)), metal material (such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), or ruthenium (Ru)), a multilayer thereof, and/or a combination thereof.

Next, multiple hard mask layers-are sequentially formed over the conductive material. The hard mask layeris made of carbon-rich material such as diamond-like carbon (DLC), High selectivity Transparency (HST), and/or spin-on coating carbon (SOC). The hard mask layeris made of semiconductor material such as polysilicon. The hard mask layeris made of silicon-rich dielectric material such as silicon-rich SiON (Si-SiON) and/or silicon-rich anti-reflective layer (Si-BARC). The hard mask layeris made of carbon-rich material such as HST, DLC, and/or SOC. The hard mask layeris a nitride layer such as silicon nitride. The hard mask layeris an oxide layer such as silicon oxide. The hard mask layeris made of semiconductor material such as polysilicon. The hard mask layeris made of carbon-rich material such as SOC, DLC, and/or HST. The hard mask layeris made of silicon-rich dielectric material such as silicon-rich anti-reflective layer (Si-BARC) and/or silicon-rich SiON (Si-SiON).

Next, a patterned photoresist layeris formed over the hard mask layerby a first photolithography process. The patterned photoresist layerhas strip patternsA that are substantially equally spaced apart from one another and are arranged in the memory cell array regionA and the peripheral circuitry regionB. In some embodiments, the first photolithography process uses an immersion coating technique.

Referring to, the semiconductor memory structureis etched using the patterned photoresist layerto sequentially etch away the portions of the hard mask layer,anduncovered by the patterned photoresist layer. The patterned photoresist layerand the hard mask layermay be entirely consumed in the etching process, or removed by an additional process such as an etching or ashing process. The etching process transfers the strip patternsA of the patterned photoresist layerinto the hard mask layersand, thereby forming patterned hard mask layersA andA. The patterned hard mask layersA andA combine to form strip patterns, which may be also referred to as core patterns.

Referring to, a spacer layeris formed along the sidewalls and the upper surface of the strip patternsand the upper surface of the hard mask layer. Next, a fill layeris formed over the spacer layerand overfills the gaps between the strip patterns. Afterward, the portions of the spacer layerand the fill layerover the upper surfaces of the strip patternsare removed to expose the patterned hard mask layerA. The spacer layeris an oxide layer such as silicon oxide. The fill layeris made of spin-on coating carbon.

Referring to, an etching process is performed to remove the portions of the spacer layeruncovered by the fill layer. The etching process further removes the portions of the hard mask layeruncovered by the fill layeruntil the hard mask layeris exposed. Because the material (e.g., SiO) of the spacer layerhas a great etching selectivity with respect to the material (e.g., SOC) of the fill layerand the hard mask layer, the etching process may remove the spacer layerin a self-aligned manner without forming an additional mask. The etching process may also recess portions of the fill layerand the patterned hard mask layerA.

After the etching process, the remaining portions of the hard mask layerare denoted asA, the remaining portions of the spacer layerare denoted asA, and the remaining portions of the fill layerare denoted asA. The patterned hard mask layerA andA and underlying hard mask layerA combine to form strip patterns. The fill layerA, the spacer layerA and the underlying hard mask layerA combine to form strip patterns.

The strip patternsandare arranged in the memory cell array regionA and the peripheral circuitry regionB. As shown in, the strip patterns(includingand) extend in a first direction Dand are substantially equally spaced apart from one another. In some embodiments, the bit lines of the memory cells extend in a second direction D, and the word lines of the memory cells extend in a third direction D. The first direction Dis not perpendicular to the second direction D, and the second direction Dis substantially perpendicular to the third direction D.

Afterward, the fill layerA and the patterned hard mask layerA may be removed.

Referring to, a photoresist patternis formed by a second photolithography process to cover the strip patternsin the periphery circuitry regionB while exposing the strip patternsin the memory cell array regionA. The photoresist patternis configured to prevent the strip patternsin the periphery circuitry regionB from being transferred into the underlying hard mask layers. In some embodiments, the second photolithography process uses an MUV (Middle ultra-violet) Mask technique which is cost-effective.

Referring to, an etching process is performed on the semiconductor memory structureusing the strip patternsand the photoresist patternto sequentially etch away the portions of the hard mask layeranduncovered by the strip patternsand the photoresist pattern. The spacer layerA and the patterned hard mask layerA in the memory cell array regionA and the photoresist patternin the periphery circuitry regionB may be entirely consumed in the etching process, or removed by an additional process. The etching process transfers the strip patternsin the memory cell array regionA into the hard mask layersandto form patterned hard mask layersA andA. The hard mask layersA andA have the strip patterns. In the periphery circuitry regionB, the strip patternsare not transferred into the hard mask layersanddue to their being covered by the photoresist pattern. The photoresist patternin the periphery circuitry regionB is transferred into the hard mask layersandto form patterned hard mask layersB andB. The patterned hard mask layersB andB combine to form a mesa pattern.

Referring to, an etching process is performed on the semiconductor memory structureto transfer the strip patternsin the memory cell array regionA into the hard mask layerto form a patterned hard mask layerA, and to transfer the mesa patternin the periphery circuitry regionB into the hard mask layerto form a patterned hard mask layerB. The patterned hard mask layersA andA in the memory cell array regionA may be entirely consumed in the etching process. Before being transferred into the patterned hard mask layerB, the strip patternsin the periphery circuitry regionB may be entirely consumed by controlling the etching process, or they may be removed by an additional process. As a result, the strip patternscan be prevented from being transferred into the mesa pattern. The mesa patternis connected to some of the strip patterns. The width of the mesa patternin the second direction Dis greater than that of a strip patternin the second direction D.

Because of the loading effect of the etching process, in the etching process, the portion of the photoresist pattern() adjacent to the boundary between the memory cell array regionA and the periphery circuitry regionB may be consumed faster than the portion of the photoresist patternfar away from the boundary. In the case where the photoresist patternhas a lower etching selectivity with respect to the hard mask layersand/or, some of the strip patternsin the periphery circuitry regionB adjacent to the boundary between regionsA andB may be also transferred into the hard mask layerand, when the strip patternsin the memory cell array regionA are transferred into the hard mask layerand. Those strip patternsin the periphery circuitry regionB may also be transferred into the hard mask layer. As a result, the wire patternsB () adjacent to the boundary between regionsA andB may suffer from the issue of pattern failure (also referred to as array punch-through).

In accordance with some embodiments of the present disclosure, because the hard mask layer(in) is a flat layer that has not been patterned, the etching amount in the memory cell array regionA may be enhanced by adjusting the parameters of the etching process (such as a greater bias RF power, higher flow rates of etchants, and/or another suitable parameter), while maintaining the photoresist patternlower etching amount. As a result, the etching selectivity between the photoresist patternand hard mask layersand/ormay increase. This may substantially reduce the risk that those strip patternsin the periphery circuitry regionB that is adjacent to the boundary between regionsA andB will be transferred into the hard mask layer. This can prevent pattern failure of the wire patternsB adjacent to the boundary between the memory cell array regionA and the periphery circuitry regionB. This can increase the manufacturing yield of the semiconductor memory device.

Afterward, the patterned hard mask layersA andB may be removed.

Referring to, a fill layeris formed over the patterned hard mask layersA andB to overfill the gaps between the patterned hard mask layersA. Next, the portion of the fill layerover the patterned hard mask layersA andB is removed to expose the patterned hard mask layersA andB. The fill layeris an oxide layer such as SiO.

Referring to, multiple hard mask layers-are sequentially formed over the patterned hard mask layersA andB and the fill layer. The hard mask layeris made of carbon-rich material such as HST, DLC, and/or SOC. The hard mask layeris a nitride layer such as silicon nitride. The hard mask layeris an oxide layer such as silicon oxide. The hard mask layeris made of semiconductor material such as polysilicon. The hard mask layeris made of carbon-rich material such as SOC, DLC, and/or HST. The hard mask layeris made of silicon-rich dielectric material such as silicon-rich anti-reflective layer (Si-BARC) and/or silicon-rich SiON (Si-SiON).

Afterward, a patterned photoresist layeris formed over the hard mask layerby a third photolithography process, as shown in. In the memory cell array regionA, the patterned photoresist layerhas strip patternsA, and dummy patternsD at the edge of the memory cell array regionA. In the periphery circuitry regionB, the patterned photoresist layerhas wire patternsB. The strip patternsA extend in the second direction Dand are substantially equally spaced apart from one another. In some embodiments, the third photolithography process uses an immersion coating technique.

Referring to, an etching process is performed on the semiconductor memory structureusing the patterned photoresist layerto sequentially etch away the portions of the hard mask layer,anduncovered by the patterned photoresist layer. The patterned photoresist layerand the hard mask layerandmay be entirely consumed in the etching process, or removed by an additional process. The etching process transfers the strip patternsA and the dummy patternsD of the patterned photoresist layerinto the hard mask layerto form a patterned hard mask layerA. The patterned hard mask layerA has strip patternsAi and dummy patterns (not shown). The wire patternsB are transferred into the hard mask layerto form a patterned hard mask layerB. The patterned hard mask layerB has wire patternsB.

Referring to, hard mask layers-are sequentially formed over the hard mask layer. The hard mask layeris made of carbon-rich material such as SOC, DLC, and/or HST. The hard mask layeris made of silicon-rich dielectric material such as silicon-rich anti-reflective layer (Si-BARC) and/or silicon-rich SiON (Si-SiON).

Afterward, a patterned photoresist layeris formed over the hard mask layerby a fourth photolithography process, as shown in. In the memory cell array regionA, the patterned photoresist layerhas strip patternsA, and dummy patternsD at the edge of the memory cell array regionA. In the periphery circuitry regionB, the patterned photoresist layerhas wire patternsB. The strip patternsA extend in the second direction Dand are substantially equally spaced apart from one another. Furthermore, the strip patternsA are staggered with the strip patternsAof the patterned hard mask layerA, and the wire patternsB are staggered with wire patternsBof the patterned hard mask layerB. In some embodiments, the fourth photolithography process uses an immersion coating technique.

Referring to, an etching process is performed on the semiconductor memory structureusing the patterned photoresist layerto sequentially etch away the portions of the hard mask layeranduncovered by the patterned photoresist layer. The patterned photoresist layermay be entirely consumed in the etching process, or removed by an additional process. The etching process transfers the strip patternsA and the dummy patternsD of the patterned photoresist layerinto the hard mask layersandto form patterned hard mask layersA andA. The patterned hard mask layersA andA have strip patternsAand the dummy patternsD. The wire patternsB are transferred into the hard mask layersandto form patterned hard mask layersB andB. The patterned hard mask layersB andB combine to form wire patternsB.

The strip patternsA (includingAandA) in the memory cell array regionA and the wire patternsB (includingBandB) in the periphery circuitry regionB are formed by two photolithography processes, which may increase the density of patterns, and thus facilitate the scaling down of the semiconductor memory device.

Referring to, an etching process is performed on the semiconductor memory structureto transfer the strip patternsA in the memory cell array regionA into the hard mask layers,andto form patterned hard mask layersA,A andA and transfer the wire patternsB in the periphery circuitry regionB into the hard mask layers,andto form patterned hard mask layersB,B andB. Although not shown, the dummy patternsD are also transferred into the hard mask layers,and. The patterned hard mask layersA,B,A,B,A, andB may be entirely consumed in the etching process, or they may be removed by an additional process.

Referring to, an etching process is performed on the semiconductor memory structureusing the strip patternsA, the dummy patternsD and the wire patternsB to etch away the portions of the patterned hard mask layersA andB and fill layeruncovered by the strip patternsA, the dummy patternsD and the wire patternsB. The patterned hard mask layersA,B,A, andB may be entirely consumed in the etching process, or removed by an additional process.

The remaining portion of the patterned hard mask layerA after the etching process is denoted asC. In the center portion of the memory cell array regionA, the strip patternsare patterned into pad patterns. At the edge of the memory cell array regionA, the strip patternsare patterned into dummy pad patternsD. The remaining portion of the fill layerafter the etching process is denoted asA. For brevity and clarity, the fill layerA is not shown in. In the periphery circuitry regionB, the etching process transfers the wire patternsB into the patterned hard mask layerB. The remaining portion of the patterned hard mask layerB is denoted asD.

In accordance with some embodiments of the present disclosure, the hard mask layeris formed by two patterning processes. In specific, the hard mask layeris patterned for the first time (by the first and the second photolithography processes) to form the strip patterns, and then the strip patternsare patterned for the second time (by the third and the fourth photolithography processes) to form the pad patterns. In some case that the hard mask layeris first patterned by the third and the fourth photolithography processes to form the strip patternsand then the strip patternsare patterned by the first and the second photolithography processes to form the pad patterns, the etching amount in the memory cell array regionA cannot be enhanced as described above inas a high etching amount may cause the pad patterns in the memory cell array region to be deformed by excessive etching. Therefore, the sequence of the process steps disclosed in the embodiments of the present disclosure may relax the window of the etching processes for forming the pad patterns.

Referring to, an etching process is performed on the semiconductor memory structureto transfer the pad patternsand the dummy pad patternsD in the memory cell array regionA into the hard mask layersandto form patterned hard mask layersA andA and to transfer the wire patternsB in the periphery circuitry regionB into the hard mask layersandto form patterned hard mask layersB andB. The patterned hard mask layersA andB may be entirely consumed in the etching process, or removed by an additional process. In addition, because the material (e.g., SiO) of the fill layerhas a greater etching selectivity with respect to the material (e.g., silicon-rich SiON), the fill layermay be removed during the etching process.

Referring to, an etching process is performed on the semiconductor memory structureto transfer the pad patternsand the dummy pad patternsD in the memory cell array regionA into the conductive materialto form conductive padsand dummy conductive padsD, and to transfer the wire patternsB in the periphery circuitry regionB into the conductive materialto form wires. The patterned hard mask layersA,B andC may be entirely consumed in the etching process, or removed by an additional process.

Afterward, the patterned hard mask layersA andB may be removed by an etching process or an ashing process, thereby exposing the conductive pads, the dummy conductive padsD and the wires. In some embodiments, capacitor structures are formed over the conductive pads. The capacitor structures may include bottom electrode layers in contact with the conductive pads, capacitor dielectric layers over the bottom electrode layers, and top electrode layers over the capacitor dielectric layers. The bottom electrode layers are electrically coupled to the source/drain regions in the active regions through the conductive padsand the contact plug.

In accordance with the embodiments of the present disclosure, by using the immersion coating technique three times and the MUV Mask technique one time, the pad patternsin the memory cell array regionA and the wire patternsB in the periphery circuitry regionB are formed at the same time. Therefore, the embodiments of the present disclosure omit one photolithography process (e.g., an immersion coating) as compared with the case where the pad patterns in the memory cell array region and the wire patterns in the peripheral circuitry region are formed separately. As a result, the manufacturing cost of the semiconductor memory structure can be saved, and the process difficulty of the semiconductor memory structure may reduce.

As described above, the embodiments of the present disclosure provide a method for forming a semiconductor memory structure that can significantly reduce the risk of the patterns in the memory cell array region being transferred into the periphery circuitry regionB. This can prevent pattern failure of the wire patterns in the periphery circuitry region adjacent to the boundary between the memory cell array region and the periphery circuitry region. This can increase the manufacturing yield of the semiconductor memory device.

While the disclosure has been described by way of example and in terms of the preferred embodiments, it should be understood that the disclosure is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.