Manufacturing method of semiconductor device

This application claims priority under 35 U.S.C. § 119(a) to Korean Patent Application No. 10-2022-0128310 filed on Oct. 7, 2022, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.

Embodiments of the present disclosure relate to an electronic device, and more particularly, to a semiconductor device and a manufacturing method thereof.

The degree of integration of a semiconductor device is mainly determined by an area occupied by a unit memory cell. Recently, as the improvement in the degree of integration of a semiconductor device for forming memory cells in a single layer on a substrate reaches a limit, a three-dimensional semiconductor device for stacking memory cells on a substrate has been proposed. Furthermore, in order to improve the operational reliability of such a semiconductor device, various structures and manufacturing methods have been developed.

In an embodiment, a manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a first seed layer in the opening; forming a first buffer layer by surface-treating the first seed layer; and forming a blocking layer by oxidizing the first seed layer through the first buffer layer.

In an embodiment, a manufacturing method of a semiconductor device may include: forming a stack comprising first material layers and second material layers that are alternately stacked; forming an opening in the stack; forming a silicon oxynitride layer in the opening; forming a first oxide layer by surface-treating the silicon oxynitride layer; forming a second oxide layer by oxidizing the silicon oxynitride layer through the first oxide layer; and forming a channel layer in the second oxide layer.

Various embodiments are directed to a semiconductor device having a stable structure and improved characteristics and a manufacturing method thereof.

By stacking memory cells in three dimensions, it is possible to improve the degree of integration of a semiconductor device. Furthermore, it is possible to provide a semiconductor device having a stable structure and improved reliability.

Hereafter, embodiments in accordance with the technical spirit of the present disclosure will be described with reference to the accompanying drawings.

andare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment.may be a plan view andmay be a cross-sectional view taken along line A-A′ in.

Referring toand, the semiconductor device may include a gate structure GST and a memory layer M. The semiconductor device may further include a channel layeror an insulating core, or a combination thereof.

The gate structure GST may be located on a lower structure, such as a source structure and a peripheral circuit. The gate structure GST may include conductive layersand insulating layersthat are alternately stacked. The conductive layersmay be a word line, a bit line, or a select line. The conductive layersmay each include a conductive material, such as polysilicon, tungsten, or molybdenum. The insulating layersmay each include an insulating material, such as oxide, nitride, or an air gap.

The channel layermay be located in the gate structure GST. The channel layermay pass through the gate structure GST in the stacking direction of the conductive layers. The channel layermay include a semiconductor material, such as silicon (Si) or germanium (Ge). A memory cell, a select transistor, or the like may be located in an area where the channel layerand the conductive layerscross each other. For reference, the semiconductor device may also include a vertical electrode instead of the channel layer.

The memory layer M may be located between the channel layerand the gate structure GST. The memory layer M may include a blocking layer, a data storage layer, or a tunneling layer, or a combination thereof. In an embodiment, the tunneling layer, the data storage layer, and the blocking layermay sequentially surround a sidewall of the channel layer.

The blocking layermay include at least one protrusion_P on an outer wall or an inner wall thereof. The protrusions_P may protrude into the gate structure GST. The protrusions_P may be located at levels respectively corresponding to the conductive layers. In an embodiment, the protrusions_P may protrude between the insulating layersto be in contact with the conductive layers, respectively. The blocking layermay include an oxide. In an embodiment, the blocking layermay be a layer that is formed by oxidizing silicon oxynitride (SiON) and may include silicon oxide (SiO).

The data storage layermay be located in the blocking layer. The data storage layermay include a floating gate, polysilicon, a charge trap material, nitride, a variable resistance material, or the like, or a combination thereof. The tunneling layermay be located in the data storage layer. The tunneling layermay include an oxide. In an embodiment, the tunneling layermay be a layer that is formed by oxidizing silicon oxynitride (SiON) and may include silicon oxide (SiO).

The insulating coremay be located in the channel layer. The insulating coremay include an insulating material, such as oxide, nitride, or air gap. For reference, the semiconductor device might not include the insulating coreand may have a shape in which the channel layeris filled up to a central area.

According to the structure described above, the semiconductor device may include stacked memory cells, and the degree of integration of the semiconductor device may be improved. Furthermore, since the memory cells include the blocking layerthat is formed by oxidizing a silicon oxynitride layer or the tunneling layerthat is formed by oxidizing a silicon oxynitride layer, operating characteristics of the memory cells may be improved.

andare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. Hereinafter, the content overlapping with the previously described content will be omitted.

Referring to, the semiconductor device may include a gate structure GST, a first memory layer M, a channel layer, or an insulating core, or a combination thereof. The gate structure GST may include conductive layersand insulating layersthat are alternately stacked. The first memory layer Mmay include a first blocking layerA, a data storage layer, or a tunneling layer, or a combination thereof.

The first blocking layerA may be a silicon oxide layer that is formed by oxidizing a silicon nitride layer. During the oxidation process, nitrogen in the silicon nitride layer may be outgassed in the form of Ngas, or nitrogen may permeate into the silicon nitride layer. Accordingly, the first blocking layerA, which is formed by using a silicon nitride layer having a relatively high nitrogen concentration as a seed layer, may include a relatively large amount of nitrogen-induced trap sites N. The trap sites N may be located in the first blocking layerA, at an interface between the first blocking layerA and the conductive layer, or at an interface between the first blocking layerA and the data storage layer. The trap sites N may cause charge loss of a memory cell.

Referring to, the semiconductor device may include a gate structure GST, a second memory layer M, a channel layer, or an insulating core, or a combination thereof. The gate structure GST may include conductive layersand insulating layersthat are alternately stacked. The second memory layer Mmay include a second blocking layerB, a data storage layer, or a tunneling layer, or a combination thereof. The second blocking layerB may be a silicon oxide layer that is formed by oxidizing a silicon oxynitride layer.

The second blocking layerB may be a silicon oxide layer that is formed by oxidizing a silicon oxynitride layer. The silicon oxynitride layer may have a lower nitrogen concentration than the silicon nitride layer. Accordingly, the second blocking layerB, which is formed by using a silicon oxynitride layer having a relatively low nitrogen concentration as a seed layer, may include a smaller amount of trap sites N than the first blocking layerA. Accordingly, charge loss of the memory cell due to the trap sites N may be minimized or prevented.

According to the structure described above, the layer quality of the blocking layersA andB may vary depending on the physical properties of a seed layer. Although both the first blocking layerA and the second blocking layerB are silicon oxide layers, the number of trap sites N that are included in the blocking layersA andB may be reduced by reducing the concentration of nitrogen that are included in the seed layer. Similarly, the number of trap sites N that are included in the tunneling layermay be reduced by reducing the concentration of nitrogen that are included in the seed layer.

andare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. Hereinafter, the content overlapping with the previously described content will be omitted.

Referring toA and, the semiconductor device may include a gate structure GST, memory layers Mand M, a channel layer, or an insulating core. The gate structure GST may include stacked conductive layers. A first memory layer Mmay include a first blocking layerA, a data storage layer, or a tunneling layer, or a combination thereof. A second memory layer Mmay include a second blocking layerB, a data storage layer, or a tunneling layer, or a combination thereof.

An opening OP may be located in the gate structure GST. The opening OP may pass through the gate structure GST in the stacking direction of the conductive layers. The opening OP may have a shape, such as a circle, an ellipse, or a polygon in plan view. However, due to process limitations or the like, at least a part of the opening OP may have an abnormal profile. The abnormal profile may indicate a shape that is different from the intended shape during an etching process. In an embodiment, in the process of forming the opening OP having a circular shape in plan view, a distorted shape, such as a circular shape having a recessed or protruding part, may be induced. Alternatively, in the process of forming the opening OP by etching layers having different etching rates, a notch may be formed at an interface between the layers.

The memory layers Mand M, the channel layer, and the insulating coremay be located in the opening OP. The first memory layer Mand the second memory layer Mmay each have a shape corresponding to the opening OP. When the opening OP has an abnormal profile, the first memory layer Mand the second memory layer Mmay each have an abnormal profile. Similarly, the channel layeror the insulating coremay each have an abnormal profile that is transferred from the opening OP.

andillustrate a difference between the profiles of the blocking layersA andB according to a difference in the concentration of nitrogen included in a seed layer. The first blocking layerA inmay be formed by oxidizing a first seed layer including nitrogen with a first concentration. The second blocking layerB inmay be formed by oxidizing a second seed layer including nitrogen with a second concentration that is different from the first concentration. The second concentration may be lower than the first concentration. In an embodiment, the first seed layer may be a nitride layer, and the second seed layer may be an oxynitride layer.

During the oxidation process, the volume expansion rate of the first seed layer may be greater than that of the second seed layer. Accordingly, a large stress may be induced in the oxidation process of the first seed layer so the first seed layer might not be sufficiently oxidized. Referring to, the opening OP may include an abnormal protrusion AB due to the abnormal profile, and a non-oxidized first seed layer SD may remain in the abnormal protrusion AB. A trap site may increase due to the remaining first seed layer SD. On the other hand, since the second seed layer has little stress in the oxidation process, the second seed layer may be sufficiently oxidized. Accordingly, the second seed layer might not remain in the abnormal protrusion AB of the opening OP, and the second blocking layerB may fill the abnormal protrusion AB.

According to the structure described above, even though the opening OP has an abnormal profile, a seed layer may be sufficiently oxidized by controlling an expansion rate according to the physical properties of the seed layer. Accordingly, the step coverage of the blocking layersA andB may be improved, and the layer quality of the blocking layers may be improved. Through this, the reliability of the semiconductor device may be improved.

toare diagrams illustrating the structure of a semiconductor device in accordance with an embodiment. Hereinafter, the content overlapping with the previously described content will be omitted.

Referring toto, the semiconductor device may include a gate structure GST, memory layers Mto M, a channel layer, or an insulating core, or a combination thereof. The gate structure GST may include conductive layersand insulating layersthat are alternately stacked. A first memory layer Mmay include a first blocking layerA, a data storage layer, or a tunneling layer, or a combination thereof, a second memory layer Mmay include a second blocking layerB, the data storage layer, or the tunneling layer, or a combination thereof, and a third memory layer Mmay include a third blocking layerC, the data storage layer, or the tunneling layer, or a combination thereof.

Referring to, the first blocking layerA of the first memory layer Mmay include substantially flat outer and inner walls. Referring to, the second blocking layerB of the second memory layer Mmay include a first protrusion_P, may include a second protrusion_P, or may include the first protrusion_Pand the second protrusion_P. The first protrusion_Pmay be located on an outer wall of the second blocking layerB, and the second protrusion_Pmay be located on an inner wall of the second blocking layerB. The first protrusion_Pand the second protrusion_Pmay be located at substantially the same level. The second protrusion_Pmay protrude into the data storage layer, and the data storage layermay have irregularities on an outer wall thereof.

Referring to, an opening OP may include at least one notch NC that is located on a sidewall thereof. The notch NC may be located at an interface between the conductive layerand the insulating layer. The notch NC may be caused by a difference in etching rates between stacked layers in the process of forming the opening OP. The notch NC may be filled with the third memory layer M. The third blocking layerC may include a protrusion_P that is located in the notch NC.

are diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. Hereinafter, the content overlapping with the previously described content will be omitted.

Referring to, a stack ST may be formed. The stack ST may be formed on a lower structure, such as a source structure and a peripheral circuit. The stack ST may include first material layersand second material layersthat are alternately stacked. The first material layersmay each include a material having a high etching selectivity with respect to the second material layers. For example, the first material layersmay each include a sacrificial material, such as nitride, and the second material layersmay each include an insulating material, such as oxide. In another example, the first material layersmay each include a conductive material, such as polysilicon, tungsten, or molybdenum, and the second material layersmay each include an insulating material, such as oxide.

Subsequently, an opening OP may be formed in the stack ST. The opening OP may have a shape, such as a circle, an ellipse, or a polygon in plan view. However, due to process limitations, at least a part of the opening OP may have an abnormal profile. In an embodiment, the opening OP may have a shape in which at least a part of a circular shape is distorted in plan view or may include at least one notch in a sidewall thereof.

In the process of forming the opening OP, oxide layersmay be formed on the first material layersthat are exposed into the opening OP. In an embodiment, the oxide layersmay be native oxide layers. The native oxide layer may be formed in an etching process for forming the opening OP or in a process of stripping a mask pattern (not illustrated) that is used to form the opening OP. The oxide layersmay be located between the second material layers. Sidewalls of the oxide layersmay be aligned with sidewalls of the second material layersor may protrude into the opening OP compared to the sidewalls of the second material layers.

Subsequently, a seed layermay be formed in the opening OP. The seed layermay be used to form a blocking layer and may include nitrogen with a relatively low concentration. In an embodiment, the seed layermay include nitrogen with a lower concentration than silicon nitride and may include silicon oxynitride. Since the seed layerwith a lower nitrogen concentration than a nitride layer is used, step coverage may be improved and oxidation degradation that is caused by loading degradation may be improved.

The seed layermay be formed along an inner surface of the opening OP. The seed layermay be formed through a deposition method, such as atomic layer deposition (ALD). When the opening OP has an abnormal profile, the seed layermay also have a profile corresponding to the abnormal profile. When the oxide layersprotrude into the opening OP to form an uneven profile, the seed layermay be formed along the uneven profile. When the opening OP includes a notch in a sidewall thereof, the seed layermay be formed in the notch.

Subsequently, a buffer layermay be formed by surface-treating the seed layer. The buffer layermay be formed by oxidizing the surface of the seed layerby a certain thickness. After the seed layeris formed, the buffer layermay be formed in-situ. The buffer layermay be a first oxide layer and may include silicon oxide. The surface of the seed layermay be oxidized by radical oxidation, and OH radicals may be used. In an embodiment, after a silicon oxynitride layer (SiON) is deposited, a silicon oxide layer (SiO) may be formed through OH radical oxidation at a low pressure in a batch.

By forming the buffer layer, the surface of the seed layermay be cured. By the curing process using radicals, impurities on the surface of the seed layermay be removed through a slow reaction, and the layer quality of a blocking layer to be formed in a subsequent process may be improved.

Referring toand, a blocking layermay be formed by oxidizing the seed layerthrough the buffer layer. After the buffer layeris formed, the blocking layermay be formed in-situ. The seed layermay be oxidized by radical oxidation, and OH radicals may be used.

In an embodiment, a second oxide layerA may be formed by oxidizing the seed layerthrough the buffer layer, and the second oxide layerA may be used as the blocking layer. Alternatively, the buffer layer(first oxide layer) and the oxide layermay be used as the blocking layer, together with the second oxide layerA. In the process of oxidizing the seed layer, the buffer layeror the oxide layermay be additionally oxidized. The blocking layermay include at least one protrusion on an outer wall or an inner wall thereof.

When the blocking layeris formed through the oxidation process, the seed layermay expand during the oxidation process, which may cause tensile stress and wafer warpage. Accordingly, a volume expansion rate may be adjusted by adjusting the nitrogen concentration of the seed layer. By forming the seed layerusing a material having a lower nitrogen concentration than a silicon nitride layer, volume expansion may be reduced, and tensile stress and wafer warpage may be reduced. By reducing trap sites due to the relatively lower nitrogen concentration in the blocking layer, charge loss may be reduced.

Furthermore, by forming the seed layerusing a material having a lower nitrogen concentration than a silicon nitride layer, oxidizing power may be increased compared to a nitride layer. Radicals may be sufficiently supplied up to a lower portion of the opening OP having a large aspect ratio, and the seed layermay be uniformly oxidized. Less oxidization of the seed layerthat is formed below the opening OP or charge loss due to trap sites may be minimized or prevented. Even though the opening OP includes a notch, the seed layerin the notch may be sufficiently oxidized and the seed layermay not be remained or less remained in the notch.

Referring to, a data storage layermay be formed in the blocking layer. The data storage layermay be formed along an inner surface of the blocking layer, and the profile of the blocking layermay be transferred to the data storage layer. The data storage layermay include irregularities on an outer wall thereof or have an abnormal profile that is transferred from the opening OP. A tunneling layermay be formed in the data storage layer. Subsequently, a channel layermay be formed in the tunneling layer. Subsequently, an insulating coremay be formed in the channel layer. The tunneling layer, the channel layer, or the insulating coremay have an abnormal profile that is transferred from the opening OP. For reference, a vertical electrode may also be formed instead of the channel layer.

Subsequently, the first material layersmay be replaced with third material layers. In an embodiment, the third material layersmay be formed after forming a slit that passes through the stack ST and removing the first material layersthrough the slit. The third material layersmay each include a metal, such as tungsten or molybdenum. Accordingly, a gate structure GST including the second material layersand the third material layersthat are alternately stacked may be formed. For reference, when each of the first material layersincludes a conductive material, such as polysilicon or metal, the first material layersmay be used as the third material layers. In such a case, a silicidation process for reducing the resistance of the first material layersmay be additionally performed.

According to the manufacturing method described above, the surface of the seed layermay be cured by forming the buffer layer, and the seed layermay be indirectly oxidized through the buffer layer. Accordingly, the layer quality of the blocking layermay be improved, and wafer warpage may be reduced. Furthermore, compared to a method of forming a blocking layer through the repeating of deposition and oxidation of a seed layer, the manufacturing cost may be reduced.

andare diagrams for describing a manufacturing method of a semiconductor device in accordance with an embodiment. Hereinafter, the content overlapping with the previously described content will be omitted.