Semiconductor device

This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2021-009377, filed Jan. 25, 2021, the entire contents of which are incorporated herein by reference.

Embodiments described herein relate generally to a semiconductor device.

For example, in the field of the liquid crystal display, such a technology has been proposed that a transistor comprising an oxide semiconductor is provided in a pixel circuit in a display area and a transistor comprising a silicon semiconductor is provided in a drive circuit in a peripheral area.

An object to the embodiments is to provide a semiconductor device which can suppress degradation in performance of the transistor.

In general, according to one embodiment, a semiconductor device comprises an insulating substrate, a first insulating layer disposed above the insulating substrate, a polycrystalline silicon semiconductor disposed on the first insulating layer, an intermediate insulating layer disposed on the polycrystalline silicon semiconductor, an oxide semiconductor disposed on the intermediate insulating layer, a second insulating layer disposed on the intermediate insulating layer and the oxide semiconductor, a gate electrode disposed on the second insulating layer and located directly above the oxide semiconductor, a first conductive layer in contact with the polycrystalline silicon semiconductor via a first contact hole penetrating the intermediate insulating layer and the second insulating layer, and in contact with the oxide semiconductor via a second contact hole penetrating the second insulating layer and a second conductive layer stacked on the first conductive layer between the first contact hole and the second contact hole, and the first conductive layer includes an extending portion extending from the second contact hole toward the gate electrode, the second conductive layer is not stacked on the extending portion, and a film thickness of the first conductive layer is less than a film thickness of the second conductive layer.

Embodiments will be described hereinafter with reference to the accompanying drawings.

Note that the disclosure is merely an example, and proper changes within the spirit of the invention, which are easily conceivable by a skilled person, are included in the scope of the invention as a matter of course. In addition, in some cases, in order to make the description clearer, the widths, thicknesses, shapes, etc., of the respective parts are schematically illustrated in the drawings, compared to the actual modes. However, the schematic illustration is merely an example, and adds no restrictions to the interpretation of the invention. Besides, in the specification and drawings, the same or similar elements as or to those described in connection with preceding drawings or those exhibiting similar functions are denoted by like reference numerals, and a detailed description thereof may be omitted unless otherwise necessary.

A semiconductor deviceof this embodiment is applicable to various display devices such as liquid crystal displays, organic electroluminescent displays, electrophoretic displays, and LED displays, as well as various sensors such as capacitive sensors and optical sensors, and other electronic devices.

is a cross-sectional view showing a configuration example of a semiconductor deviceof this embodiment.

The semiconductor devicehas a base, insulating layersto, transistors TRand TR, and a connection electrode CN. For example, the insulating layercorresponds to the first insulating layer, the insulating layerstocorrespond to an intermediate insulating layers, the insulating layercorresponds to the second insulating layer, and the insulating layercorresponds to the third insulating layer.

The transistor TRcomprises a semiconductor (first semiconductor) SCand a gate electrode GE. The semiconductor SCis, for example, a polycrystalline silicon semiconductor, but it may be some other silicon-based semiconductor. The gate electrode GEis an electrode electrically connected to a gate line.

The transistor TRcomprises a semiconductor SC(second semiconductor) and a gate electrode GE. The semiconductor SCis, for example, an oxide semiconductor. The gate electrode GEis an electrode electrically connected to a gate line.

The connection electrode CN is an electrode that electrically connects the transistor TRand the transistor TRdirectly to each other. The connection electrode CN functions as either one of the source electrode or the drain electrode of the transistor TR. The connection electrode CN also functions as either one of the source electrode and drain electrode of the transistor TR. Note that in the transistor TR, an electrode connected to an opposite side thereof to the connection electrode CN while interposing the gate electrode GEtherebetween (that is, the other one of the source electrode and the drain electrode) is omitted from the illustration. Further, in the transistor TR, an electrode connected to an opposite side thereof to the connection electrode CN while interposing the gate electrode GEtherebetween (that is, the other one of the source electrode and the drain electrode) is omitted from the illustration.

The baseis an insulating substrate and is formed of an insulating material such as glass, resin film or the like. The insulating layeris disposed above the base.

The semiconductor SCis disposed above the insulating layer. The insulating layeris disposed above the insulating layerand covers the semiconductor SC.

The gate electrode GEis located directly above the semiconductor SC, disposed on the insulating layerand covered by the insulating layer. A light-shielding layer LS is provided to correspond to the transistor TR, disposed on the insulating layerand covered by the insulating layer. In other words, the gate electrode GEand the light-shielding layer LS are metal layers located in the same layer and formed of the same material. The insulating layeris disposed on the insulating layer.

The semiconductor SCis located directly above the light-shielding layer LS and disposed on the insulating layer. The insulating layeris disposed on the insulating layerand covers the semiconductor SC. In other words, in the example shown in, the insulating layersto, which are intermediate insulating layers, are interposed between the semiconductor SCand the semiconductor SC. The intermediate insulating layers are disposed on the semiconductor SCand the semiconductor SCis disposed on the intermediate insulating layers.

The gate electrode GEis located directly above the semiconductor SCand is disposed on the insulating layer. The gate electrode GEis at the same potential as that of the light-shielding layer LS, for example. The connection electrode CN is located above the insulating layer. In other words, the gate electrode GEand the connection electrode CN are metal layers located in the same layer and formed of the same material.

The connection electrode CN is electrically connected to the semiconductor SCin a first contact hole CHwhich penetrates the insulating layersto. Further, the connection electrode CN is electrically connected as well to the semiconductor SCin a second contact hole CHwhich penetrates the insulating layer.

The connection electrode CN is constituted by a stacked body of the first conductive layer Land the second conductive layer L. The second conductive layer Lis stacked on the first conductive layer L. The first conductive layer Lis in contact with the semiconductor SCvia the first contact hole CH, and also in contact with the semiconductor SCvia the second contact hole CH. Further, the first conductive layer Lincludes an extending portion EX which extends from a position in contact with the semiconductor SCin the first contact hole CHtoward the gate electrode GE.

The second conductive layer Lis stacked on the first conductive layer Lbetween the first contact hole CHand the second contact hole CH. In the example shown in, the second conductive layer Lfurther extends to the transistor TRand is stacked on the first conductive layer Lin the first contact hole CH. The second conductive layer Lis not in contact with the semiconductor SCin the first contact hole CH. An end surface Sof the second conductive layer Lon a transistor TRside is located on a gate electrode GEside with respect to the position overlapping the first contact hole CH.

On the other hand, the second conductive layer Ldoes not extend to the transistor TRand is not stacked on the first conductive layer Lin the second contact hole CH. That is, an end surface Sof the second conductive layer Lon a transistor TRside does not overlap the second contact hole CH. Further, the second conductive layer Lis not stacked on the extending portion EX.

The gate electrode GEis configured as a stacked body similar to that of the connection electrode CN. That is, the gate electrode GEcomprises a first layer Lformed of the same material as that of the first conductive layer L, and a second layer Lformed of the same material as that of the second conductive layer L. The second layer Lis stacked on the first layer L.

Directly above the insulating layer, a film thickness Tof the first conductive layer Lis less than a film thickness Tof the second conductive layer L(T<T). The film thickness Tof the second conductive layer Lis three times or more than the film thickness Tof the first conductive layer L. For example, the film thickness Tis about 30 nm and the film thickness Tis Tis about 100 nm.

The first conductive layer Lis formed of a material different from that of the second conductive layer L. In selecting the material for each of the first and second conductive layers, it is desirable that the density of the material which forms the first conductive layer Lis lower than the density of the material which forms the second conductive layer L. For example, the material of the first conductive layer Lcontains at least one of titanium (Ti) and aluminum (Al), and the material of the second conductive layer Lcontains at least one of molybdenum (Mo) and tungsten (W).

However, since the first conductive layer Lis in contact with the semiconductor SC, which is an oxide semiconductor, it is desirable that it be formed of a material that is not easily oxidized. For example, the first conductive layer Lshould preferably be a single layer of titanium-based material or a stacked body in which an aluminum-based layer is stacked on a titanium-based layer.

The insulating layerstoare, for example, transparent inorganic insulating layers formed of silicon nitride (SiN), silicon oxide (SiO) and the like. The insulating layerstomay each be a single layer formed of a single insulating material or may be a stacked body formed from multiple insulating materials.

For example, the insulating layeris a stacked body of a silicon nitride and a silicon oxide, the insulating layeris formed of silicon oxide, the insulating layeris formed of silicon nitride, and the insulating layersandare formed of silicon oxide.

Next, an example of a method of manufacturing the transistors TRand TRshown inwill be described.

illustrate the method of manufacturing the transistors TRand TR. In the cross-sectional views shown in, the baseis omitted from the illustration.

First, as shown in, the insulating layer, the semiconductor (polycrystalline silicon semiconductor) SC, the insulating layer, the gate electrode GE, the light-shielding layer LS, the insulating layersand, the semiconductor (oxide semiconductor) SCand the insulating layerare formed in order.

Note that, before forming the semiconductor SC, an impurity is implanted to the semiconductor SCusing the gate electrode GEas a mask. Here, the impurity implanted is, for example, phosphorus (P) in the case of n-channel type, whereas boron (B) in the case of p-channel type.

After forming insulating layer, the first contact hole CHwhich penetrates the insulating layerstoto the semiconductor SC, and the second contact hole CHwhich penetrates the insulating layerto the semiconductor SCare formed. In the first contact hole CH, a part of the semiconductor SCis exposed, and in the second contact hole CH, a part of the semiconductor SCis exposed.

Then, as shown in, a metal film is formed on the insulating layer, and the metal film is patterned, thus forming the first conductive layer Lof the connection electrode CN and the first layer Lof the gate electrode GE. The first conductive layer Lis in contact with the semiconductor SCin the first contact hole CH, and in contact with the semiconductor SCin the second contact hole CH, and further includes an extending portion EX. The first layer Lis located directly above the semiconductor SCand is spaced apart from the first conductive layer L. In the region of the semiconductor SC, which is in contact with the first conductive layer L, oxygen is absorbed by the first conductive layer L, thus lowering the resistance.

Next, as shown in, after forming a metal film, the metal film is patterned, thus forming the second conductive layer Lof the connection electrode CN and the second layer Lof the gate electrode GE. The second conductive layer Loverlaps the first conductive layer Lin the first contact hole CH, and further overlaps the first conductive layer Lbetween the first contact hole CHand the second contact hole CH. The second layer Loverlaps the first layer Land is spaced apart from the second conductive layer L.

Subsequently, as shown in, ion implantation is carried out on the semiconductor SCusing the gate electrode GEas a mask. For example, boron (B) is implanted to the semiconductor SCas the impurity by the ion implantation. In place of boron, some other impurity such as phosphorus (P) may be implanted to the semiconductor SC.

In such ion implantation, the second conductive layer Land the second layer L, which have relatively high-density and is relatively thick, have a high ability to block the implantation of impurities. Therefore, in the region directly under the gate electrode GE, which is a stacked body of the first layer Land the second layer L, substantially no impurities are implanted.

On the other hand, impurities are implanted to the region directly under the first conductive layer L, which is thin and the region where the insulating layeris exposed. Especially, the first conductive layer Lis formed of a relatively low-density material, and therefore, impurities easily permeate therethrough. With this configuration, impurities can be easily implanted to, for example, the region directly below the extending portion EX, including the region where the insulating layeris covered only by the first conductive layer L. Therefore, in the semiconductor SC, impurities are implanted to the region directly under the extending portion EX and the region between the first conductive layer Land the gate electrode GE, and thus the resistance of these regions are lowered.

Incidentally, as described above, when the transistor TRis of an n-channel type, the impurity to be implanted to the semiconductor SCis phosphorus. Here, when boron is to be implanted as an impurity to the semiconductor SC, the impurity contained in the semiconductor SCis different in type from that of the semiconductor SC. Therefore, when implanting an impurity to the semiconductor SC, it is necessary to protect the semiconductor SCfrom being implanted with the impurity (boron). Thus, in the first contact hole CH, the second conductive layer Lis stacked on the first conductive layer L.

Further, as in the case where the semiconductor SCof the p-channel transistor TRcontains boron as an impurity and phosphorus is to be implanted as an impurity to the semiconductor SC, for the purpose of suppressing undesired impurities from being implanted to the semiconductor SC, the second conductive layer Lis stacked on the first conductive layer Lin the first contact hole CH.

In the case where the impurity contained in the semiconductor SCis the same in type as that of the semiconductor SC, the second conductive layer Lof the first contact hole CHmay be omitted. For example, in the case where the impurity contained in the semiconductor SCis phosphorus and phosphorus is to be implanted as an impurity to the semiconductor SC, or the case where the impurity contained in the semiconductor SCis boron and boron is to be implanted as an impurity to the semiconductor SC, the second conductive layer Lof the first contact hole CHmay be omitted.

is a cross-sectional view showing the semiconductor SCafter implanting the impurity.

The semiconductor SCincludes regions Ato A. Each of these regions will now be described in detail.

The region (first region) Ais located directly under the gate electrode GE. The region (second region) Ais located directly under the extending portion EX. The region (third region) Ais located between the region Aand the region Aand is connected to the regions Aand A. The region Ais located on an opposite side to the region Awhile interposing the region Atherebetween. In other words, the region Ais located between the region Aand the region A, and is connected to the regions Aand A. The region Aand the region Aoverlap the region of the insulating layer, which is exposed from the first conductive layer Land the first layer L. The region Ais a region in contact with the first conductive layer Lin the second contact hole CH.

The impurity concentration of each of the regions Ato Ais higher than that of the region A. Note that the impurity concentrations of the regions Ato Aare substantially equal to each other. For example, boron (B) is implanted as an impurity in each of the regions Ato A, whereas in the region A, boron (B) is no substantially implanted. That is, the region Acorresponds to the channel region of the semiconductor SC. The impurity concentration in this specification can be expressed as the number of impurity ions (atoms) per unit volume. Note that as to oxide semiconductors, a high impurity concentration means a large number of oxygen defects per unit volume or a large number of defects per unit volume.

From another point of view, in the semiconductor SC, the regions Ato Aeach have a resistance lower than that of the region A. The resistance values of the regions Ato Aare substantially equal to each other. The region Ais in contact with the first conductive layer L, and has a resistance even lower than that of the region A.

Next, the impurity concentrations in portions Pand Pencircled by dotted lines in the cross-sectional view shown inwere calculated by simulation. In this simulation, the concentration of boron was calculated as the impurity concentration.

The portion Pis a region where the extending portion EX of the first conductive layer L, the insulating layer, the region Aof the semiconductor SCand the insulating layerare stacked.

The portion Pis a region where the first conductive layer Lis not formed and further the insulating layer, the region Aof the semiconductor SCand the insulating layerare stacked.

is a diagram showing results of the first simulation. Here, the acceleration energy at the time of the ion implantation is set to 30 keV, and the ion dosage is set to 1×10ions/cm.