Chip scale semiconductor package having back side metal layer and raised front side pad and method of making the same

This invention relates generally to a chip scale semiconductor package having a back side metal layer and raised front side pads and a method of making the chip scale semiconductor package. More particularly, the present invention relates to a chip scale power semiconductor package having each of the raised front side pads comprising a copper member and a solder member.

A conventional chip scale power semiconductor package comprises flat pads causing printed circuit board (PCB) level soldering issues thereby increasing the chance that the conventional chip scale power semiconductor package being peeled off from the PCB.

The present disclosure introduces raised pads to improve PCB level soldering reliability. Each of the raised pads comprises a copper member and a solder member thereby increasing wettable area during a solder reflow process and increasing a space for forming the under-fill process. A thick metal layer, in a range from 25 microns to 50 microns, improves electrical performance. Optional molding compound layers further improves mechanical strength of the chip scale semiconductor package.

The present invention discloses a chip scale semiconductor package comprising a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member.

The present invention discloses a method for fabricating a chip scale semiconductor package. The method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.

shows a perspective view of a chip scale semiconductor packagein examples of the present disclosure. In one example, the chip scale semiconductor packageis a common drain power semiconductor package. The chip scale semiconductor packagehas a front sideand a back side. The chip scale semiconductor packagecomprises a silicon layer, a back side metal layer, and a plurality of front side pads. In one example, the silicon layercomprises a first MOSFET transistor and a second MOSFET transistor formed thereon. Each of the first MOSFET transistor and the second MOSFET transistor comprises a gate region and a source region on a front side of the silicon layer, and a drain region at a back side of the silicon layeropposite the front side. The back side metal layer forms a common drain electrode of the first MOSFET and second MOSFET. The plurality of frond side padsinclude a first gate pad connecting to a first gate metalof the first MOSFET, one or more first source pads connecting to a first source metalof the first MOSFET, and a second gate pad connecting to a second gate metalof the second MOSFET, one or more second source pads connecting to a second source metalof the second MOSFET. Each of the plurality of front side padscomprises a respective copper memberand a respective solder member. A back surfaceB of the respective solder memberis directly attached to a front surfaceF of the respective copper member.

In one example, a thickness of the respective copper memberof each of the plurality of front side padsis in a range from 25 microns to 50 microns. A thickness of the respective solder memberof each of the plurality of front side padsis in a range from 1 micron to 5 microns. A thickness of the silicon layeris in a range from 30 microns to 100 microns. The first gate metal, the first source metal, the second gate metaland the second source metalare electrically connected to the gate regions and source regions of the first and second MOSFET transistors respectively and may be formed by patterning a front metal layer of Aluminum or Aluminum alloy overlaying the front side of the silicon layer. A front surface of the front metal layer forms the outermost front surface of the chip scale semiconductor package. A passivation layer may overlay a periphery of each of the first gate metal, the first source metal, the second gate metal and the second source metal. The copper member of each front side pad extends from a front surface of the front metal layer up to a height in a range from 25 microns to 50 microns. In one example, the respective solder membercomprises Sn. In another example, the respective solder membercomprises Sn and Ni. In still another example, the respective solder membercomprises Sn, Ni, and Au.

shows a perspective view of a chip scale semiconductor packagein examples of the present disclosure. The chip scale semiconductor packagecomprises a silicon layer, a back side metal layer, a plurality of front side pads, and a molding compound layerdirectly attached to a back sideB of the back side metal layer.

shows a perspective view of a chip scale semiconductor packagein examples of the present disclosure. The chip scale semiconductor packagecomprises a silicon layer, a back side metal layer, a plurality of front side pads, a first molding compound layerattached to a front sideF of the silicon layer, and a second molding compound layerdirectly attached to a back sideB of the back side metal layer. A front surface of the first molding compound layerforms the outermost front surface of the chip scale semiconductor package. The copper member of each front side pad extends from a front surface of the front metal layer up to a height above the outermost front surface.

shows a perspective view of a chip scale semiconductor packagein examples of the present disclosure. The chip scale semiconductor packagecomprises a silicon layer, a back side metal layer, a plurality of front side pads, and a molding compound layerattached to a front sideF of the silicon layer. A front surface of the first molding compound layerforms the outermost front surface of the chip scale semiconductor package. The copper member of each front side pad extends from a front surface of the front metal layer up to a height above the outermost front surface.

shows a cross-sectional view of a chip scale semiconductor packageattached to a PCBin examples of the present disclosure. The chip scale semiconductor packagecomprises a plurality of front side padsconnected to connection pads on the PCB. Each of the plurality of front side padscomprises a respective copper memberand a respective solder member. After a solder reflow process, additional respective solderdirectly contacts a sidewallof the respective copper memberof each of the plurality of front side pads. In one example, the additional respective solderis of a tapered shape having larger horizontal dimension toward the PCBand smaller horizontal dimension toward the back side of the respective copper member. The respective solder memberof each of the plurality of front side padsdirectly contacts a corresponding connection pad on the PCB. The chip scale semiconductor packagemay be one of chip scale semiconductor package shown in.

An under-fill layerpositioned between an outermost front surface of the chip scale semiconductor packageand the PCB. In order to properly apply the under-fill layer, a minimum distance between the outermost front surface of the chip scale semiconductor packageand the PCBis required. The minimum distance (for example, larger than 5 microns) is larger than the thickness of the solder memberof each of the plurality of front side pads, that is, for example, in a range from 1 micron to 5 microns.

A front surface areaof the respective copper memberof each of the plurality of front side padsis smaller than a surface areaof a respective connection pad of the plurality of connection pads of the PCB.

is a flowchart of a processto develop a plurality of chip scale semiconductor packages in examples of the present disclosure.show the cross sections of the corresponding steps. The processmay start from block.

In block, referring now to, a waferis provided. The wafercomprises a front sideand a back sideopposite the front side. In one example, the waferis a silicon wafer comprising a plurality of semiconductor devices formed thereon each comprising a front metal layer patterned into a plurality of front electrodes (not shown). The wafermay be a 4-inch, 6-inch, 8-inch, 12-inch, or 18-inch diameter wafer. Blockmay be followed by block.

In block, referring now to, a grinding process is applied to the back sideof the waferso as to thin the waferfrom its backside. In one example, the grinding process is only applied to a center portion of the back sideof the waferso as to form a recessand a peripheral ring. The recessis of a cylinder shape. The peripheral ringis of a circular ring shape. The peripheral ringmay be a Taiko ring. The peripheral ringprovides required strength to support the wafer under the metallization process in block. Blockmay be followed by block.

In block, referring now to, a metallization process is applied so as to form a metal layerin the recess. The metal layeris deposited to the back side of the wafer. In one example, the metal layeris made of copper. Blockmay be followed by block.

In block, referring now to, the peripheral ring(in one example, the Taiko ring) is removed so as to form a flat, circular, back surface. The metal layercovers an entire back surface of the thinned layer. Blockmay be followed by blockor block.

In optional block(shown in dashed lines), referring now to, a molding compound layeroverlaying the metal layeris formed. In one example, the molding compound material is different from a lamination compound material. Blockmay be followed by block.

In block, referring now to, a front side conductive seed layeris formed on the front side of the wafer on top of the patterned front metal layer (before forming the front side seed layer, the wafer is flipped so that the front side is on top). Blockmay be followed by block.

In block, referring now to, a front side photoresist layeris formed covering the seed layer. Blockmay be followed by block.

In block, referring now to, a photolithography process is applied so as to form a patternto selectively expose areas of the seed layersiting on each front electrode formed by the patterned front metal layer. Blockmay be followed by block.

In block, referring now to, a front side copper plating process is applied so as to form a plurality of copper memberson the exposed seed layer area electrically connected the respective front electrode. Blockmay be followed by block.

In block, referring now to, a front side solder plating process is applied so as to form a plurality of solder memberson top of each copper members. Blockmay be followed by block.

In block, referring now to, the front side photoresist layeris stripped so as to expose areas of the front side seed layernot covered by the copper member. Blockmay be followed by block.

In block, referring now to, the exposed front side seed layeris etched. The plurality of solder membersare on top of the plurality of copper members. Blockmay be followed by block.

In block, referring now to, a singulation process is applied so as to from a plurality of chip scale semiconductor packages. Without performing the optional block, each of the plurality of chip scale semiconductor packagesis the chip scale semiconductor packageof. Including performing the optional block, each of the plurality of chip scale semiconductor packagesis the chip scale semiconductor packageof.

is a flowchart of a processto develop a plurality of chip scale semiconductor packages in examples of the present disclosure.show the cross sections of the corresponding steps. The processis similar to the processexcept that the step of forming a front side seed layer and the step of forming a front side photoresist layer are before the step of grinding a back side of the wafer. The processmay start from block.

In block, referring now to, a waferis provided. The wafercomprises a front sideand a back sideopposite the front side. In one example, the waferis a silicon wafer comprising a plurality of semiconductor devices formed thereon each comprising a front metal layer patterned into a plurality of front electrodes (not shown). The wafermay be a 4-inch, 6-inch, 8-inch, 12-inch, or 18-inch diameter wafer. Blockmay be followed by block.

In block, referring now to, a front side conductive seed layeris formed on the front side of the wafer on top of the patterned front metal layer. Blockmay be followed by block.

In block, referring now to, a front side photoresist layeris formed covering the seed layer. Blockmay be followed by block.

In block, referring now to, a grinding process is applied to the back sideof the waferso as to thin the waferfrom its backside (before applying the grinding process, the wafer is flipped so that the back side is on top). In one example, the grinding process is only applied to a center portion of the back sideof the waferso as to form a recessand a peripheral ring. The recessis of a cylinder shape. The peripheral ringis of a circular ring shape. The peripheral ringmay be a Taiko ring. The peripheral ringprovides required strength to support the wafer under the metallization process in block. Blockmay be followed by block.

In block, referring now to, a metallization process is applied so as to form a metal layerin the recess. The metal layeris deposited to the back side of the wafer. In one example, the metal layeris made of copper. Blockmay be followed by block.

In block, referring now to, the peripheral ring(in one example, the Taiko ring) is removed so as to form a flat, circular, back surface. The metal layercovers an entire back surface of the thinned layer. Blockmay be followed by blockor block.

In optional block(shown in dashed lines), referring now to, a molding compound layeroverlaying the metal layeris formed. In one example, the molding compound material is different from a lamination compound material. Blockmay be followed by block.

In block, referring now to, a photolithography process is applied so as to form a patternto selectively expose areas of the seed layersiting on each front electrode formed by the patterned front metal layer (before applying the photolithography process, the wafer is flipped so that the front side is on top). Blockmay be followed by block.

In block, referring now to, a front side copper plating process is applied so as to form a plurality of copper memberson the exposed seed layer area electrically connected to the respective front electrode. Blockmay be followed by block.

In block, referring now to, a front side solder plating process is applied so as to form a plurality of solder members. Blockmay be followed by block.

In block, referring now to, the front side photoresist layeris stripped so as to expose areas of the front side seed layernot covered by the copper members. Blockmay be followed by block.

In block, referring now to, the exposed front side seed layeris etched. The plurality of solder membersare on top of the plurality of copper members. Blockmay be followed by block.

In block, referring now to, a singulation process is applied so as to from a plurality of chip scale semiconductor packages.

is a flowchart of a processto develop a plurality of chip scale semiconductor packages in examples of the present disclosure.show the cross sections of the corresponding steps. The processis similar to the processexcept that the step of applying a photolithography process, the step of applying a front side copper plating process, and the step of applying a front side solder plating process are after the step of removing a peripheral ring. The processmay start from block.

In block, referring now to, a waferis provided. The wafercomprises a front sideand a back sideopposite the front side. In one example, the waferis a silicon wafer comprising a plurality of semiconductor devices formed thereon each comprising a front metal layer patterned into a plurality of front electrodes (not shown). The wafermay be a 4-inch, 6-inch, 8-inch, 12-inch, or 18-inch diameter wafer. Blockmay be followed by block.

In block, referring now to, a front side conductive seed layeris formed on the front side of the wafer on top of the patterned front metal layer. Blockmay be followed by block.

In block, referring now to, a front side photoresist layeris formed covering the seed layer. Blockmay be followed by block.

In block, referring now to, a photolithography process is applied so as to form a patternto selectively expose areas of the seed layersiting on each front electrode formed by the patterned front metal layer. Blockmay be followed by block.

In block, referring now to, a front side copper plating process is applied so as to form a plurality of copper memberson the exposed seed layer area electrically connected to the respective front electrode. Blockmay be followed by block.

In block, referring now to, a front side solder plating process is applied so as to form a plurality of solder members. Blockmay be followed by block.

In block, referring now to, a grinding process is applied to the back sideof the waferso as to thin the waferfrom its backside (before applying the grinding process, the wafer is flipped so that the back side is on top). In one example, the grinding process is only applied to a center portion of the back sideof the waferso as to form a recessand a peripheral ring. The recessis of a cylinder shape. The peripheral ringis of a circular ring shape. The peripheral ringmay be a Taiko ring. The peripheral ringprovides required strength to support the wafer under the metallization process in block. Blockmay be followed by block.

In block, referring now to, a metallization process is applied so as to form a metal layerin the recess. The metal layeris deposited to the back side of the wafer. In one example, the metal layeris made of copper. Blockmay be followed by block.